From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 34FF33858D33; Wed, 19 Apr 2023 19:18:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 34FF33858D33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681931900; bh=x3NJYDC3t2tG/y+YG1bA38V3qu7Im73LYleskZdP9Vw=; h=From:To:Subject:Date:From; b=gb/HVhFU5O7WFjiXsC58pzeL+KZtwttc2fBmD5lTzLg3a8Keuto6huvq6ryYzUF2q WOShRr2jGqhFeM8JNlC+Rk91euewNX6ZafcQ3BSvQaqUYLmswsoMiXXRIWU93DB6R1 hWP79G+IbIZt1FRuQpe82uGX/jnna+r3fGTBK6OI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 5e229034bf8bb04c66b694f108a8eeaa05a72160 X-Git-Newrev: 2ecd33ae0e474e043aa8b509ba2bc0af1cbc8597 Message-Id: <20230419191820.34FF33858D33@sourceware.org> Date: Wed, 19 Apr 2023 19:18:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2ecd33ae0e474e043aa8b509ba2bc0af1cbc8597 commit 2ecd33ae0e474e043aa8b509ba2bc0af1cbc8597 Author: Michael Meissner Date: Wed Apr 19 15:16:48 2023 -0400 Combine vec_extract of V4SF with DF convert. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. 2023-04-18 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn. Diff: --- gcc/config/rs6000/vsx.md | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0e681844243..c3b870640ed 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3951,23 +3957,28 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number. +;; If the element number is 0, we don't need to do a load immediate operation. +;; Likewise for GPRs with offsettable loads, we can fold the offset into the +;; address. For vector registers, we are limited to X-FORM memory addresses. +;; PowerPC64 is needed because we need a DI temporary base register. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=r,r,r,,") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") + (parallel [(match_operand:QI 2 "" "0,n,n,0,n")]))) + (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,load,load,fpload,fpload") + (set_attr "length" "4,4,8,4,8") + (set_attr "isa" "*,*,*,,")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"