From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id F19A83858D33; Wed, 19 Apr 2023 19:32:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F19A83858D33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681932771; bh=sPnxQ76fRDyLvX1sIDv7U9UFm2e/i0ce0rLZaBf754k=; h=From:To:Subject:Date:From; b=NlHrQle/2K57JfeUdS/++voMoeXp8CiZGn367l/aeon4pPlaoyEAHe0CWH9HqhlM0 ThHS1p5WZZMkNrJqua75U0oAaf4pC0pY9nQ0idcgUejQiA9NksFM4ddyAoRmvDnd2E rtI+ClPspKbo0Rck1D36/h698oZ1CGT2iMFGmA1E= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 113f76a81ff56d0ed3ec318dc088b31ac34c8934 X-Git-Newrev: 189afb0d76cb331f3754c586133a2ea3982e1342 Message-Id: <20230419193251.F19A83858D33@sourceware.org> Date: Wed, 19 Apr 2023 19:32:51 +0000 (GMT) List-Id: https://gcc.gnu.org/g:189afb0d76cb331f3754c586133a2ea3982e1342 commit 189afb0d76cb331f3754c586133a2ea3982e1342 Author: Michael Meissner Date: Wed Apr 19 15:32:35 2023 -0400 Combine vec_extract of V4SF with DF convert. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. 2023-04-18 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 417aff5e24b..ebc986fc6ac 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3567,6 +3567,27 @@ (set_attr "length" "8") (set_attr "isa" "*,p7v,p9v,*")]) +;; V4SF extract from memory and convert to DFmode with constant element number +(define_insn_and_split "*vsx_extract_v4sf_to_df_load" + [(set (match_operand:DF 0 "register_operand" "=f,v") + (float_extend:DF + (vec_select:SF + (match_operand:V4SF 1 "memory_operand" "m,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))) + (clobber (match_scratch:P 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (float_extend:DF (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8") + (set_attr "isa" "*,p8v")]) + ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")