From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id C80EF3858D37; Fri, 21 Apr 2023 03:12:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C80EF3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682046726; bh=wM/dYLXAZ/RpWIrhmJv3OmEkEUjGPff7+ufMcjmx6B0=; h=From:To:Subject:Date:From; b=YLuJdtPD0SfXktF9eKtA3Wu+lM5jaYq5ibUkL27EUaDBRnjntxOH2MOljec71rlFB EeC6TepaeO7p8xe5PoA6Rlqci0vLYwE7WW0OGWs2bdMs5Vtk8vBPzR3TpL3A+EyigW k0GAsL5Je+WPPBG0f4jzqYLZWCGsK12vzvC4h/Gk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: ce7a90c0c0b37c320993c5ccab8f6de271a9be09 X-Git-Newrev: 0c9e5ca8705c37db519064652aec3b649e32ba50 Message-Id: <20230421031206.C80EF3858D37@sourceware.org> Date: Fri, 21 Apr 2023 03:12:06 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0c9e5ca8705c37db519064652aec3b649e32ba50 commit 0c9e5ca8705c37db519064652aec3b649e32ba50 Author: Michael Meissner Date: Thu Apr 20 23:11:50 2023 -0400 Allow vec_extract with variable element number to load vector registers. 2023-04-20 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load): Allow vec_extract of integer types with a variable element number to load into vector registers. Allow splitting before register allocation. Diff: --- gcc/config/rs6000/vsx.md | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c5c2920fcd1..fd17d0c29f1 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4124,21 +4124,23 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,r,,") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m") + (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "4,8,4,8") + (set_attr "isa" "*,*,,")]) ;; ISA 3.1 extract (define_expand "vextractl"