From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 59DD83858D37; Fri, 21 Apr 2023 04:05:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 59DD83858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682049938; bh=s3LGBQOWKevd0kzeCz+3i1YZr1nCrYZLwsn4ieMjkjc=; h=From:To:Subject:Date:From; b=m4qR6m+8cK1deiDlmN/58LxNadxpW0GrQPYkZIgtAJGTIgmvi12UBZN15B07NighS w6YcTU9A5rEikwP9Stj6cd/9ofsDqUgbZabQSSHG8iyM2d3FTAUYocaJkfO4FnZgJs bDpxQG5Bn2PN1kVUKxiO1XBQ140gEeHRjXQ6a/rQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: cbad65bd5d95dcabcf8d72dc0b71e85c4d67f806 X-Git-Newrev: 5dddad51364149a704e8271379b0962b4bcf6790 Message-Id: <20230421040538.59DD83858D37@sourceware.org> Date: Fri, 21 Apr 2023 04:05:38 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5dddad51364149a704e8271379b0962b4bcf6790 commit 5dddad51364149a704e8271379b0962b4bcf6790 Author: Michael Meissner Date: Fri Apr 21 00:05:19 2023 -0400 Allow vec_extract with variable element number to load vector registers. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load): Allow vec_extract of integer types with a variable element number to load into vector registers. Allow splitting before register allocation. Diff: --- gcc/config/rs6000/vsx.md | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index b234b807087..d6b72a2fe33 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4127,21 +4127,23 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,r,,") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m") + (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "12,16,12,16") + (set_attr "isa" "*,*,,")]) ;; ISA 3.1 extract (define_expand "vextractl"