From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 4D0EE3858C50; Fri, 21 Apr 2023 15:36:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4D0EE3858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682091378; bh=X9rA7ps+E9dHQ3FNVJgO+byc9sxAFoxSZg5ovNpPumo=; h=From:To:Subject:Date:From; b=GYng/pTK5YLDn0d/qEQca1eXfqkb4LM/E5OjHXit1mOmTJr0caA3qgiNZG76KfsV+ PfPZ/5xZCui3VjJ4pvuxJAc+Z+ECIYYlI+rr4TtalsZ7Mn1XeaolPvrnuSEkyZfitn WqDW4FKesDpJxz57ujTq2YuGZ9HMS1QbDnH9bsCU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 9e52adf2cb3b591b176548c68fd15a70bd42b530 X-Git-Newrev: a1f248363949c5533957524329b5a600f06c1dac Message-Id: <20230421153618.4D0EE3858C50@sourceware.org> Date: Fri, 21 Apr 2023 15:36:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a1f248363949c5533957524329b5a600f06c1dac commit a1f248363949c5533957524329b5a600f06c1dac Author: Michael Meissner Date: Fri Apr 21 11:36:14 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 30 ---------------------- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 5 +--- .../gcc.target/powerpc/vec-extract-mem-int-4.c | 27 ------------------- 3 files changed, 1 insertion(+), 61 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 457513a4eaa..3364a0791c2 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4214,36 +4214,6 @@ (set_attr "length" "12,16,16,20") (set_attr "isa" "*,*,p9v,p9v")]) -;; Extract a V4SI element from memory with variable element number and convert -;; it to SFmode or DFmode using either signed or unsigned conversion. -(define_insn_and_split "*vsx_extract_v4si_load_to_" - [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") - (any_float:SFDF - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b")) - (clobber (match_scratch:DI 4 "=f,v"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 4) - (match_dup 5)) - (set (match_dup 0) - (float:SFDF (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2], - operands[3], SImode); - operands[5] = gen_rtx_ (DImode, new_mem); -} - [(set_attr "type" "fpload") - (set_attr "length" "20") - (set_attr "isa" "*,p8v")]) - ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c index 17db9bbe107..437001a6177 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c @@ -22,8 +22,5 @@ extract_uns_v4si_var (vector unsigned int *p, size_t n) /* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ /* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ - -/* There are 2 rldicl's to make the variable element number, but there is not a - third one to do the zero extension. */ /* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c deleted file mode 100644 index 415dee36d8a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - SImode and convert the value to float, and double by loading the value - directly into a vector register, and not loading up the GPRs first. */ - -#include -#include - -float -extract_float_sign_v4si_var (vector int *p, size_t n) -{ - return vec_extract (*p, n); /* lfiwax or lxsiwax. */ -} - -double -extract_double_uns_v4si_var (vector unsigned int *p, size_t n) -{ - return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */ -} - -/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */