From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 6639C385840C; Fri, 21 Apr 2023 15:40:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6639C385840C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682091650; bh=GUT7k/ZhKlOXDeIdlfvgwpEG6rEcAiq2UaY88UiwXHw=; h=From:To:Subject:Date:From; b=g8DYAtOHO1RcbYPImB85DBL5ydnshHEP8BAmguJJNer86G4XReguk0v87TSoad6uF dOJVBQErtm9CfTBKdfiYoHALZLbw8CHrPulPymiCEFGR/+huRAbGd2A7bm41FYLePE kZDmMB977sTOOTd/fcE+OMu149o8c11hwbmePDuA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold sign or zero extension into vsx_extract from memory with variable element. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: a616f64dd3f782f8ef7a0fca48d8de7fce7a0309 X-Git-Newrev: 11d2085d9127b313e2898ded2bd4fa355487dc0e Message-Id: <20230421154050.6639C385840C@sourceware.org> Date: Fri, 21 Apr 2023 15:40:50 +0000 (GMT) List-Id: https://gcc.gnu.org/g:11d2085d9127b313e2898ded2bd4fa355487dc0e commit 11d2085d9127b313e2898ded2bd4fa355487dc0e Author: Michael Meissner Date: Fri Apr 21 11:40:33 2023 -0400 Fold sign or zero extension into vsx_extract from memory with variable element. This patch folds conversion to floating point of vsx_extract from memory of V4SI elements where the element number is constant. This code optimizes things so it will load the integer with LFIWAX or LFIWZX directly into a vector register rather than loading it into a GPR and doing a direct move operation. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-int-4.c: New file. Diff: --- gcc/config/rs6000/vsx.md | 30 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-4.c | 27 +++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 3364a0791c2..457513a4eaa 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4214,6 +4214,36 @@ (set_attr "length" "12,16,16,20") (set_attr "isa" "*,*,p9v,p9v")]) +;; Extract a V4SI element from memory with variable element number and convert +;; it to SFmode or DFmode using either signed or unsigned conversion. +(define_insn_and_split "*vsx_extract_v4si_load_to_" + [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") + (any_float:SFDF + (unspec:SI + [(match_operand:V4SI 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b")) + (clobber (match_scratch:DI 4 "=f,v"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64" + "#" + "&& 1" + [(set (match_dup 4) + (match_dup 5)) + (set (match_dup 0) + (float:SFDF (match_dup 4)))] +{ + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (DImode); + + rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2], + operands[3], SImode); + operands[5] = gen_rtx_ (DImode, new_mem); +} + [(set_attr "type" "fpload") + (set_attr "length" "20") + (set_attr "isa" "*,p8v")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c new file mode 100644 index 00000000000..415dee36d8a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ + +/* Test to verify that the vec_extract with variable element numbers can load + SImode and convert the value to float, and double by loading the value + directly into a vector register, and not loading up the GPRs first. */ + +#include +#include + +float +extract_float_sign_v4si_var (vector int *p, size_t n) +{ + return vec_extract (*p, n); /* lfiwax or lxsiwax. */ +} + +double +extract_double_uns_v4si_var (vector unsigned int *p, size_t n) +{ + return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */ +} + +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */