From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 822273857732; Fri, 21 Apr 2023 18:10:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 822273857732 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682100649; bh=lW71GAtShK6yui5avD0/YzNJPsYEFFibc+YyyTgdHDo=; h=From:To:Subject:Date:From; b=yn/CU9P7n9vXWmD4JvHBF5r4R6KU2bkoFcLX+joRa04yJgECMpNWJ66V182Jmokzm s5bEs11ZDR6yIhZwhbuoNwldDX6tyzKej+GbiXYJlCAFeRFYshiZL04ppGJ9tNUDXy DcuWRY/QFth/H/dAELbH9g1mMVU5bvL02Kfu5f0g= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 11d2085d9127b313e2898ded2bd4fa355487dc0e X-Git-Newrev: 5c39e42356b13392ac03dc4a73dc4a7ea2e2e3cf Message-Id: <20230421181049.822273857732@sourceware.org> Date: Fri, 21 Apr 2023 18:10:49 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5c39e42356b13392ac03dc4a73dc4a7ea2e2e3cf commit 5c39e42356b13392ac03dc4a73dc4a7ea2e2e3cf Author: Michael Meissner Date: Fri Apr 21 14:10:45 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/rs6000.cc | 56 ++-- gcc/config/rs6000/vsx.md | 290 ++------------------- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 22 -- .../gcc.target/powerpc/vec-extract-mem-char-2.c | 17 -- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 37 --- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 38 --- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 30 --- .../gcc.target/powerpc/vec-extract-mem-int-4.c | 27 -- .../gcc.target/powerpc/vec-extract-mem-short-1.c | 37 --- .../gcc.target/powerpc/vec-extract-mem-short-2.c | 26 -- 10 files changed, 33 insertions(+), 547 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 65295dbaf81..3be5860dd9b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -7686,13 +7686,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (CONST_INT_P (element)) return GEN_INT (INTVAL (element) * scalar_size); - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - - /* After register allocation, all insns should use the 'Q' constraint - (address is a single register) if the element number is not a - constant. */ - gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem)); + /* All insns should use the 'Q' constraint (address is a single register) if + the element number is not a constant. */ + gcc_assert (satisfies_constraint_Q (mem)); /* Mask the element to make sure the element number is between 0 and the maximum number of elements - 1 so that we don't generate an address @@ -7708,9 +7704,6 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (shift > 0) { rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift)); - if (can_create_pseudo_p ()) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, shift_op)); } @@ -7754,9 +7747,6 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) else { - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7779,8 +7769,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) temporary (BASE_TMP) to fixup the address. Return the new memory address that is valid for reads or writes to a given register (SCALAR_REG). - The temporary BASE_TMP might be set multiple times with this code if this is - called after register allocation. */ + This function is expected to be called after reload is completed when we are + splitting insns. The temporary BASE_TMP might be set multiple times with + this code. */ rtx rs6000_adjust_vec_address (rtx scalar_reg, @@ -7793,11 +7784,8 @@ rs6000_adjust_vec_address (rtx scalar_reg, rtx addr = XEXP (mem, 0); rtx new_addr; - if (GET_CODE (base_tmp) != SCRATCH) - { - gcc_assert (!reg_mentioned_p (base_tmp, addr)); - gcc_assert (!reg_mentioned_p (base_tmp, element)); - } + gcc_assert (!reg_mentioned_p (base_tmp, addr)); + gcc_assert (!reg_mentioned_p (base_tmp, element)); /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); @@ -7853,9 +7841,6 @@ rs6000_adjust_vec_address (rtx scalar_reg, offset, it has the benefit that if D-FORM instructions are allowed, the offset is part of the memory access to the vector element. */ - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1))); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7863,33 +7848,26 @@ rs6000_adjust_vec_address (rtx scalar_reg, else { - if (GET_CODE (base_tmp) == SCRATCH) - base_tmp = gen_reg_rtx (Pmode); - emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } - /* If register allocation has been done and the address isn't valid, move - the address into the temporary base register. Some reasons it could not - be valid include: + /* If the address isn't valid, move the address into the temporary base + register. Some reasons it could not be valid include: The address offset overflowed the 16 or 34 bit offset size; We need to use a DS-FORM load, and the bottom 2 bits are non-zero; We need to use a DQ-FORM load, and the bottom 4 bits are non-zero; Only X_FORM loads can be done, and the address is D_FORM. */ - if (!can_create_pseudo_p ()) - { - enum insn_form iform - = address_to_insn_form (new_addr, scalar_mode, - reg_to_non_prefixed (scalar_reg, scalar_mode)); + enum insn_form iform + = address_to_insn_form (new_addr, scalar_mode, + reg_to_non_prefixed (scalar_reg, scalar_mode)); - if (iform == INSN_FORM_BAD) - { - emit_move_insn (base_tmp, new_addr); - new_addr = base_tmp; - } + if (iform == INSN_FORM_BAD) + { + emit_move_insn (base_tmp, new_addr); + new_addr = base_tmp; } return change_address (mem, scalar_mode, new_addr); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 457513a4eaa..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -207,10 +207,6 @@ (define_mode_iterator VSX_EXTRACT_I2 [V16QI V8HI]) (define_mode_iterator VSX_EXTRACT_I4 [V16QI V8HI V4SI V2DI]) -;; Iterator for vector extract/insert of small integer vectors that can be sign -;; extended with the load. -(define_mode_iterator VSX_EXTRACT_ISIGN [V8HI V4SI]) - (define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b") (V8HI "h") (V4SI "w")]) @@ -227,12 +223,6 @@ (V8HI "v") (V4SI "wa")]) -;; Mode attribute to give the isa constraint for accessing Altivec registers -;; with vector extract and insert operations. -(define_mode_attr VSX_EX_ISA [(V16QI "p9v") - (V8HI "p9v") - (V4SI "p8v")]) - ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -251,10 +241,6 @@ (TF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (TFmode)")]) -;; Whether to use SIGN or ZERO when depending on the floating point conversion. -(define_code_attr SIGN_ZERO_EXTEND [(float "SIGN_EXTEND") - (unsigned_float "ZERO_EXTEND")]) - ;; Iterator for the 2 short vector types to do a splat from an integer (define_mode_iterator VSX_SPLAT_I [V16QI V8HI]) @@ -3581,27 +3567,6 @@ (set_attr "length" "8") (set_attr "isa" "*,p7v,p9v,*")]) -;; V4SF extract from memory and convert to DFmode with constant element number -(define_insn_and_split "*vsx_extract_v4sf_to_df_load" - [(set (match_operand:DF 0 "register_operand" "=f,v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))) - (clobber (match_scratch:P 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8") - (set_attr "isa" "*,p8v")]) - ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") @@ -3637,27 +3602,6 @@ } [(set_attr "type" "fpload,load")]) -;; Combine V4SF extract from memory with a variable element number with -;; conversion to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "12")]) - ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") @@ -3986,124 +3930,23 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element -;; number. If the element number is 0, we don't need to do a load immediate -;; operation. Likewise for GPRs with offsettable loads, we can fold the offset -;; into the address. For loading to vector registers, we are limited to X-FORM -;; memory addresses. We need TARGET_POWERPC64 because we are creating a DI -;; base register temporary. +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r,r,r,,") - (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,n,0,n")]))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" + [(set (match_operand: 0 "register_operand" "=r") + (vec_select: + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,8,4,8") - (set_attr "isa" "*,*,*,,")]) - -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number -;; and zero extend it to DImode. -(define_insn_and_split "*vsx_extract__load_to_udi" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,,") - (zero_extend:DI - (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,n,0,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,8,4,8") - (set_attr "isa" "*,*,*,,")]) - -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number -;; and sign extend it to DImode. -(define_insn_and_split "*vsx_extract__load_to_sdi" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,,") - (sign_extend:DI - (vec_select: - (match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "" "0,n,n,0,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,12,8,12") - (set_attr "isa" "*,*,*,,")]) - -;; Extract a V8HI element from memory with a constant element number -;; and zero or sign extend it to SImode. -(define_insn_and_split "*vsx_extract_v8hi_load_to_si" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,v,v") - (any_extend:SI - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_7_operand" "0,n,n,0,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:SI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], HImode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,12,8,12") - (set_attr "isa" "*,*,*,p9v,p9v")]) - -;; Extract a V4SI element from memory with constant element number and convert -;; it to SFmode or DFmode using either signed or unsigned conversion. -(define_insn_and_split "*vsx_extract_v4si_load_to_" - [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") - (any_float:SFDF - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))) - (clobber (match_scratch:DI 3 "=&b,&b")) - (clobber (match_scratch:DI 4 "=f,v"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 4) - (match_dup 5)) - (set (match_dup 0) - (float:SFDF (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2], - operands[3], SImode); - operands[5] = gen_rtx_ (DImode, new_mem); -} - [(set_attr "type" "fpload") - (set_attr "length" "12") - (set_attr "isa" "*,p8v")]) + [(set_attr "type" "load") + (set_attr "length" "8")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" @@ -4127,122 +3970,21 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r,r,,") + [(set (match_operand: 0 "gpc_reg_operand" "=r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "12,16,12,16") - (set_attr "isa" "*,*,,")]) - -;; Extract a V16QI/V8HI/V4SI element from memory with a variable element number -;; and zero extend it to DImode. -(define_insn_and_split "*vsx_extract__var_load_to_udi" - [(set (match_operand:DI 0 "register_operand" "=r,r,,") - (zero_extend:DI - (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "12,16,12,16") - (set_attr "isa" "*,*,,")]) - -;; Extract a V8HI/V4SI element from memory with a variable element number -;; and sign extend it to DImode. -(define_insn_and_split "*vsx_extract__var_load_to_sdi" - [(set (match_operand:DI 0 "register_operand" "=r,r,,") - (sign_extend:DI - (unspec: - [(match_operand:VSX_EXTRACT_ISIGN 1 "memory_operand" "Q,m,Q,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "12,16,12,16") - (set_attr "isa" "*,*,,")]) - -;; Extract a V8HI element from memory with a variable element number -;; and zero or sign extend it to SImode. -(define_insn_and_split "*vsx_extract_v8hi_var_load_to_si" - [(set (match_operand:SI 0 "register_operand" "=r,r,v,v") - (any_extend:SI - (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:SI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], HImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "12,16,16,20") - (set_attr "isa" "*,*,p9v,p9v")]) - -;; Extract a V4SI element from memory with variable element number and convert -;; it to SFmode or DFmode using either signed or unsigned conversion. -(define_insn_and_split "*vsx_extract_v4si_load_to_" - [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") - (any_float:SFDF - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b")) - (clobber (match_scratch:DI 4 "=f,v"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64" - "#" - "&& 1" - [(set (match_dup 4) - (match_dup 5)) - (set (match_dup 0) - (float:SFDF (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2], - operands[3], SImode); - operands[5] = gen_rtx_ (DImode, new_mem); -} - [(set_attr "type" "fpload") - (set_attr "length" "20") - (set_attr "isa" "*,p8v")]) + [(set_attr "type" "load")]) ;; ISA 3.1 extract (define_expand "vextractl" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index fa75c4c2a83..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,22 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold the sign/extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c deleted file mode 100644 index ee6fb79993a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c +++ /dev/null @@ -1,17 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - QImode and fold the zero extension into the load. */ - -#include -#include - -unsigned long long -extract_uns_var_v16qi (vector unsigned char *p, size_t n) -{ - return vec_extract (*p, n); /* lbzx, no rlwinm. */ -} - -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index e81ab4954ae..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index 91e85bf5a5b..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,38 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and convert the value to float, and double by loading the value - directly into a vector register, and not loading up the GPRs first. */ - -#include - -float -extract_float_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lfiwax or lxsiwax. */ -} - -float -extract_float_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lfiwax or lxsiwax. */ -} - -double -extract_double_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lfiwzx or lxsiwzx. */ -} - -double -extract_double_uns_v4si_3 (vector unsigned int *p) -{ - return vec_extract (*p, 3); /* lfiwzx or lxsiwzx. */ -} - -/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c deleted file mode 100644 index c4413fc158f..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - SImode and fold the sign/extension into the load. */ - -#include -#include - -long long -extract_sign_v4si_var (vector int *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -unsigned long long -extract_uns_v4si_var (vector unsigned int *p, size_t n) -{ - return vec_extract (*p, n); /* lwzx, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ - -/* There are 2 rldicl's to ensure the variable element number is between 0..3, - but there is not a third one to do the zero extension after the unsigned - int load. */ -/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c deleted file mode 100644 index 415dee36d8a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - SImode and convert the value to float, and double by loading the value - directly into a vector register, and not loading up the GPRs first. */ - -#include -#include - -float -extract_float_sign_v4si_var (vector int *p, size_t n) -{ - return vec_extract (*p, n); /* lfiwax or lxsiwax. */ -} - -double -extract_double_uns_v4si_var (vector unsigned int *p, size_t n) -{ - return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */ -} - -/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index 19b7d879065..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c deleted file mode 100644 index efb5447f11b..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c +++ /dev/null @@ -1,26 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - HImode and fold the sign/extension into the load. */ - -#include -#include - -long long -extract_sign_v8hi_var (vector short *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -unsigned long long -extract_uns_v8hi_var (vector unsigned short *p, size_t n) -{ - return vec_extract (*p, n); /* lwzx, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlhax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlhzx\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */