From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 7224B3858D20; Fri, 21 Apr 2023 19:35:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7224B3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682105730; bh=SVBgIUIrBWTcX26d+9XvpT0EPl3V2hTZLGFa9Qyhk1k=; h=From:To:Subject:Date:From; b=iwPS6FBf1Da+6OgcSHPUVblOJy2i4Nuutam7euSy4T4kix2Cg7eKxmk9riML9qdQy z6ip3A8NTScSECz6NBUJ334BDncFF2gNtiW7UM62iJyjXFcTxVt2cDvbseMoHHo0Qk NmhRaNSrpoikuEm/xRmWUXLxBT0EgmlZjRynUk2I= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 5a5c396c1052046c96e5e823eee80c05ef53b0a5 X-Git-Newrev: d39233a0c7fc59c314e54fbacba3d8018e0fc7ba Message-Id: <20230421193530.7224B3858D20@sourceware.org> Date: Fri, 21 Apr 2023 19:35:30 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d39233a0c7fc59c314e54fbacba3d8018e0fc7ba commit d39233a0c7fc59c314e54fbacba3d8018e0fc7ba Author: Michael Meissner Date: Fri Apr 21 15:35:09 2023 -0400 Improve vec_extract of V4SF with variable element number. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is variable combined with a conversion to DFmode. In addition, I changed the vec_extract of V4SFmode where the element number is variable without conversion to do the split before register allocation. I also set the length attribute for the length before the split is done. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before register allocation. (vsx_extract_v4sf_var_load_to_df): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-float-2.c: New test. Diff: --- gcc/config/rs6000/vsx.md | 31 ++++++++++++++++++---- .../gcc.target/powerpc/vec-extract-mem-float-2.c | 27 +++++++++++++++++++ 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c3848de5d4f..ea29df72ccc 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3607,22 +3607,43 @@ DONE; }) -;; Variable V4SF extract from memory +;; V4SF extract from memory with variable element number. (define_insn_and_split "*vsx_extract_v4sf_var_load" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r") (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q") (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" + (clobber (match_scratch:P 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode)" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" "fpload,load")]) + [(set_attr "type" "fpload,load") + (set_attr "length" "12")]) + +;; V4SF extract from memory and convert to DFmode with variable element number. +(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" + [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") + (float_extend:DF + (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:P 3 "=&b"))] + "VECTOR_MEM_VSX_P (V4SFmode)" + "#" + "&& 1" + [(set (match_dup 0) + (float_extend:DF (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload") + (set_attr "length" "12")]) ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c new file mode 100644 index 00000000000..af66fd20c21 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx" } */ + +/* Test to verify that the vec_extract with variable element numbers can load + float (SF) variables directly using a single LFSX or LXSSPX instruction. */ + +#include +#include + +float +extract_float_var (vector float *p, size_t n) +{ + return vec_extract (*p, n); /* lfsx or lxsspx. */ +} + +double +extract_float_to_double_var (vector float *p, size_t n) +{ + return vec_extract (*p, n); /* lfsx or lxsspx. */ +} + +/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */ +/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */ +/* { dg-final { scan-assembler-not {\mvslo\M} } } */ +/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */