From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 4D48F3858D20; Fri, 21 Apr 2023 19:36:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4D48F3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682105796; bh=BfQux7xN2M0i1qu23Kcx2Yj6aCDE/cd/+T1lQ/Syed0=; h=From:To:Subject:Date:From; b=pQWZk7S8n2m+/Q1afxk6rsTNSE3nfJtC/OY6D7d6f/NcbH1b/bBrKLr/hpjJBVkDP uelayKchrJZXkqFwLDD4r7P1AmuAKQXIJEWlt/+iypU0URyMAz2Iaa7Y1AtFJKBHbi Q3ucxL53u5T/1M9Lnea2VaQE5PqEe2ph4bJoRrIE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: d39233a0c7fc59c314e54fbacba3d8018e0fc7ba X-Git-Newrev: f5002e5626c8c6502fc6a377965a9424aa6160bc Message-Id: <20230421193636.4D48F3858D20@sourceware.org> Date: Fri, 21 Apr 2023 19:36:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f5002e5626c8c6502fc6a377965a9424aa6160bc commit f5002e5626c8c6502fc6a377965a9424aa6160bc Author: Michael Meissner Date: Fri Apr 21 15:36:32 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 55 +++------------------- .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 ------------ .../gcc.target/powerpc/vec-extract-mem-float-2.c | 27 ----------- 3 files changed, 6 insertions(+), 105 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ea29df72ccc..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3549,7 +3549,6 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory convert to DFmode with constant element number. (define_insn_and_split "*vsx_extract_v4sf_load" [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF @@ -3558,7 +3557,7 @@ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], @@ -3568,27 +3567,6 @@ (set_attr "length" "8") (set_attr "isa" "*,p7v,p9v,*")]) -;; V4SF extract from memory and convert to DFmode with constant element number. -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" "=f,v,v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,Z,m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))) - (clobber (match_scratch:P 3 "=&b,&b,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& 1" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8") - (set_attr "isa" "*,p7v,p9v")]) - ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") @@ -3607,43 +3585,22 @@ DONE; }) -;; V4SF extract from memory with variable element number. +;; Variable V4SF extract from memory (define_insn_and_split "*vsx_extract_v4sf_var_load" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r") (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q") (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:P 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" "fpload,load") - (set_attr "length" "12")]) - -;; V4SF extract from memory and convert to DFmode with variable element number. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:P 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& 1" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "12")]) + [(set_attr "type" "fpload,load")]) ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index eab7892ed80..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-O2 -mvsx" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float (SF) variables into a GPR without doing a LFS or STFS. */ - -#include - -float -extract_float_0_gpr (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ ("# %0" : "+r" (x)); /* lwz. */ - *q = x; -} - -float -extract_float_3_gpr (vector float *p, float *q) -{ - float x = vec_extract (*p, 3); - __asm__ ("# %0" : "+r" (x)); /* lwz. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c deleted file mode 100644 index af66fd20c21..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-O2 -mvsx" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - float (SF) variables directly using a single LFSX or LXSSPX instruction. */ - -#include -#include - -float -extract_float_var (vector float *p, size_t n) -{ - return vec_extract (*p, n); /* lfsx or lxsspx. */ -} - -double -extract_float_to_double_var (vector float *p, size_t n) -{ - return vec_extract (*p, n); /* lfsx or lxsspx. */ -} - -/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */ -/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */ -/* { dg-final { scan-assembler-not {\mvslo\M} } } */ -/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */