From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id AC53E3858C74; Fri, 21 Apr 2023 19:55:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AC53E3858C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682106933; bh=kDROIWcGGzhmPgMr9yq4TEMlTFYM4IT9x70JQN4I9zA=; h=From:To:Subject:Date:From; b=AqmyrWaixl+Y/49QAiRwB18E8p+bNfCI8mBHPlHIYo3igvhpKOC4HfFbskMvs2d9P KsI4CqeyBx1wAhWTDq3prasL+qYnxQfbtNoKrKv6SEfG3bQvO2fb6GRcCBrpNKdOhy SFrNGHJjoL4KCGuOz4DUEqyJNdxhM67Sb9UWG9Ew= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: a456d1d3ed62f2659381ee32be723dbc73ae6f03 X-Git-Newrev: bb3324da2b643fa18dacd9b6e7554e991dca0d35 Message-Id: <20230421195533.AC53E3858C74@sourceware.org> Date: Fri, 21 Apr 2023 19:55:33 +0000 (GMT) List-Id: https://gcc.gnu.org/g:bb3324da2b643fa18dacd9b6e7554e991dca0d35 commit bb3324da2b643fa18dacd9b6e7554e991dca0d35 Author: Michael Meissner Date: Fri Apr 21 15:55:18 2023 -0400 Combine vec_extract of V4SF with DF convert. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. In addition, I changed the vec_extract of V4SFmode where the element number is constant without conversion to do the split before register allocation. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before register allocation. (vsx_extract_v4sf_to_df_load): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-float-1.c: New test. Diff: --- gcc/config/rs6000/vsx.md | 24 ++++++++++++++- .../gcc.target/powerpc/vec-extract-mem-float-1.c | 36 ++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 417aff5e24b..c3848de5d4f 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3549,6 +3549,7 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) +;; V4SF extract from memory convert to DFmode with constant element number. (define_insn_and_split "*vsx_extract_v4sf_load" [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF @@ -3557,7 +3558,7 @@ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], @@ -3567,6 +3568,27 @@ (set_attr "length" "8") (set_attr "isa" "*,p7v,p9v,*")]) +;; V4SF extract from memory and convert to DFmode with constant element number. +(define_insn_and_split "*vsx_extract_v4sf_load_to_df" + [(set (match_operand:DF 0 "register_operand" "=f,v,v") + (float_extend:DF + (vec_select:SF + (match_operand:V4SF 1 "memory_operand" "m,Z,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))) + (clobber (match_scratch:P 3 "=&b,&b,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode)" + "#" + "&& 1" + [(set (match_dup 0) + (float_extend:DF (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8") + (set_attr "isa" "*,p7v,p9v")]) + ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c new file mode 100644 index 00000000000..e110d308307 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + float (SF) variables into a GPR without doing a LFS or STFS. + + Target LP64 and power8 vector are needed because the compiler only does the + vec_extract optimizations on 64-bit machines that have direct move support. + On earlier machines, vec_extract is done by storing the V4SF value into + memory, and just doing the load from memory. */ + +#include + +float +extract_float_0_gpr (vector float *p, float *q) +{ + float x = vec_extract (*p, 0); + __asm__ ("# %0" : "+r" (x)); /* lwz. */ + *q = x; +} + +float +extract_float_3_gpr (vector float *p, float *q) +{ + float x = vec_extract (*p, 3); + __asm__ ("# %0" : "+r" (x)); /* lwz. */ + *q = x; +} + +/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */ +/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */ +/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */ +/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */