[gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:b356c9b29a749d29281daa1ebfd973ea69c3271b

commit b356c9b29a749d29281daa1ebfd973ea69c3271b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 18:00:51 2023 -0400

    Improve vec_extract of V4SF with variable element number.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is variable combined with a conversion to DFmode.
    
    I also modified the insn for vec_extract of V4SFmode where the element number is
    variable to split before register allocation.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_var_load_to_df): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-2.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 21 ++++++++++++++++++-
 .../gcc.target/powerpc/vec-extract-mem-float-2.c   | 24 ++++++++++++++++++++++
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 17e56ab1ce4..1141e7b9fa7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3616,7 +3616,7 @@
    (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,6 +3624,25 @@
 }
   [(set_attr "type" "fpload,load")])
 
+;; V4SF extract from memory with variable element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+	(float_extend:DF
+	 (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+		     (match_operand:DI 2 "gpc_reg_operand" "r")]
+		    UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")])
+
 ;; Expand the builtin form of xxpermdi to canonical rtl.
 (define_expand "vsx_xxpermdi_<mode>"
   [(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..65107ee0c74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+void
+extract_float_0_gpr (vector float *p, float *q, size_t n)
+{
+  float x = vec_extract (*p, n);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               1 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              1 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mm[tf]vsd}              } } */
+/* { dg-final { scan-assembler-not   {\mxscvdpspn?\M}          } } */