From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 5663C3858D20; Fri, 21 Apr 2023 22:02:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5663C3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682114541; bh=TpOu6C6a8yacF9nXV6/hXmMhU4kg7INnMMhVtW9k5UY=; h=From:To:Subject:Date:From; b=BqUNs3ql9YFEbscK7uORI5jx8zOsZEi49J48jifhvXOlSmxWRcICU8As9ZV+s5kk4 6NKJI3FB0h2gSFKTirkHqamN5ugnv+Z1jwiMpAq0uX3PqiJRCMyhL165fjxonym34e 3t/S+HXrYNJB8/nT+MfmjnchhBCq4I1NEBZUHVLU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: b356c9b29a749d29281daa1ebfd973ea69c3271b X-Git-Newrev: ef1242f0cfa9c773050c6cebb5770d3152409fef Message-Id: <20230421220221.5663C3858D20@sourceware.org> Date: Fri, 21 Apr 2023 22:02:21 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ef1242f0cfa9c773050c6cebb5770d3152409fef commit ef1242f0cfa9c773050c6cebb5770d3152409fef Author: Michael Meissner Date: Fri Apr 21 18:02:18 2023 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 82745912b34..61634f875b1 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,25 @@ +==================== Branch work119, patch #52 ==================== + +Improve vec_extract of V4SF with variable element number. + +This patch adds a combine insn that merges loading up a vec_extract of V4SFmode +where the element number is variable combined with a conversion to DFmode. + +I also modified the insn for vec_extract of V4SFmode where the element number is +variable to split before register allocation. + +2023-04-21 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before + register allocation. + (vsx_extract_v4sf_var_load_to_df): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-float-2.c: New test. + ==================== Branch work119, patch #51 ==================== Combine vec_extract of V4SF with DF convert. @@ -6,7 +28,8 @@ This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. In addition, I changed the vec_extract of V4SFmode where the element number is -constant without conversion to do the split before register allocation. +constant without conversion to do the split before register allocation. I also +simplified the alternatives. 2023-04-21 Michael Meissner