From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 7A9B53858C83; Fri, 21 Apr 2023 23:48:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A9B53858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682120934; bh=gXoPR5B9faeGeZC79KJIw8+R4Xi6BL+VyxyUim5NooQ=; h=From:To:Subject:Date:From; b=WNZQDwdJfzXitgamUN4BMfDOhdT146SQHSDV6zzIZxBJX+LgUOVEmBei92A1Gmb5p TftamUjY9aiLOlwkMjl/qe1U1Nw3pfIjarlMz5BDJ7WRNpM4yszSAxv81nhoUA/6cE FPRlMJug1LAa72w+rFu3XSx52u7tqZ7lpdo7jzQ4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 9c8fe27948dc1b000cb4d8d75e7b2bd8e876d297 X-Git-Newrev: b7348c952a9cbc0b3bc9402c2e9187c4ea763c48 Message-Id: <20230421234854.7A9B53858C83@sourceware.org> Date: Fri, 21 Apr 2023 23:48:54 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b7348c952a9cbc0b3bc9402c2e9187c4ea763c48 commit b7348c952a9cbc0b3bc9402c2e9187c4ea763c48 Author: Michael Meissner Date: Fri Apr 21 19:48:36 2023 -0400 Allow integer vec_extract to load vector registers. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute (vsx_extract__load): Allow vec_extract of integer types with a constant element number to load into vector registers. Don't require a base register temporary if the element number is 0. Diff: --- gcc/config/rs6000/vsx.md | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 04877dd51f6..9d76217f84c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3971,13 +3977,15 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element +;; number. If the element number is 0, we don't need a temporary base +;; register. For vector registers, we require X-form addressing. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=r,r,,") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q,Z,Q") + (parallel [(match_operand:QI 2 "" "O,n,O,n")]))) + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3986,8 +3994,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "8") + (set_attr "isa" "*,*,,")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"