From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 9218E3858D20; Sat, 22 Apr 2023 00:21:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9218E3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682122915; bh=31QWr7Plg5Oxsemt6keezbZohUEHJY4FaZWie2+ogLA=; h=From:To:Subject:Date:From; b=do1nvAMUA60xkoXn7O5wnCKMJdRbtetImyOzdjjMyTbWj4pDHN3KOrjk92y8f+PvV d/pFtfM9lcwzGfMuRMW6XP4a4Qryb6/Ms23UpRIOb/6ujd5XLTYYjxN1J0NJ7UIg3w EiW9aB9H7GWXw1CKR4lP2ZiEwUJoRjB3PfbW7ws8= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold V4SI sign or zero extension into vsx_extract from memory with constant element. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: b7348c952a9cbc0b3bc9402c2e9187c4ea763c48 X-Git-Newrev: b6ab178f9557cc172f19350b6c68f1b7027abb82 Message-Id: <20230422002155.9218E3858D20@sourceware.org> Date: Sat, 22 Apr 2023 00:21:55 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b6ab178f9557cc172f19350b6c68f1b7027abb82 commit b6ab178f9557cc172f19350b6c68f1b7027abb82 Author: Michael Meissner Date: Fri Apr 21 20:21:35 2023 -0400 Fold V4SI sign or zero extension into vsx_extract from memory with constant element. This patch folds V4SI vsx_extract from memory where the element number is constant with sign or zero extension to DImode. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_load_to_di): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 9d76217f84c..5fb77e9cc22 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3998,6 +3998,27 @@ (set_attr "length" "8") (set_attr "isa" "*,*,,")]) +;; Extract a V4SI element from memory with a constant element number and sign +;; or zero extend it to DImode. +(define_insn_and_split "*vsx_extract_v4si_load_to_di" + [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa") + (any_extend:DI + (vec_select:SI + (match_operand:V4SI 1 "memory_operand" "m,Q,Z,Q") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))) + (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:DI (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SImode); +} + [(set_attr "type" "load,load,fpload,fpload") + (set_attr "length" "8")]) + ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r")