From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 525933858D20; Sat, 22 Apr 2023 00:48:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 525933858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682124507; bh=cm/AZkAu+erz1ue7KAB5A4yCqAHjUbv0qsAa2PHvpbc=; h=From:To:Subject:Date:From; b=bu24R56o+mVbDi5zMUEsy+6t2BQnCTEapVH2NidA/LF63GINkjTEVTFLwRauHhthM DA8WczwBtzerWqY/NXQcXl4nOYNR7XQzGwsn+ei5X+KIqOyhvCJB9EW0ZayEL3c+p5 MxTMpic2f2RJzIRVBK3yUp0wAgADlAb60zpj4Y9w= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold sign/zero extension into V8HI vsx_extract from memory with constant element. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: b6ab178f9557cc172f19350b6c68f1b7027abb82 X-Git-Newrev: 58533ad32aa7aaaaf05cad5ff340337e60a4c406 Message-Id: <20230422004827.525933858D20@sourceware.org> Date: Sat, 22 Apr 2023 00:48:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:58533ad32aa7aaaaf05cad5ff340337e60a4c406 commit 58533ad32aa7aaaaf05cad5ff340337e60a4c406 Author: Michael Meissner Date: Fri Apr 21 20:47:55 2023 -0400 Fold sign/zero extension into V8HI vsx_extract from memory with constant element. This patch folds V8HI vsx_extract from memory where the element number is constant with sign or zero extension to SImode/DImode. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v8hi_load_to_): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 5fb77e9cc22..8e9c9955139 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4019,6 +4019,27 @@ [(set_attr "type" "load,load,fpload,fpload") (set_attr "length" "8")]) +;; Extract a V8HI element from memory with a constant element number and sign +;; or zero extend it to either SImode or DImode. +(define_insn_and_split "*vsx_extract_v8hi_load_to_" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (any_extend:GPR + (vec_select:HI + (match_operand:V8HI 1 "memory_operand" "m,Q") + (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")])))) + (clobber (match_scratch:DI 3 "=X,&b"))] + "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], HImode); +} + [(set_attr "type" "load") + (set_attr "length" "8")]) + ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r")