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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Add vec_extract test cases.
Date: Sat, 22 Apr 2023 00:57:04 +0000 (GMT)	[thread overview]
Message-ID: <20230422005704.CFF6B3858C83@sourceware.org> (raw)

https://gcc.gnu.org/g:d0bc01e34e067428b4afa710ae92f00f63e272f9

commit d0bc01e34e067428b4afa710ae92f00f63e272f9
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 20:56:46 2023 -0400

    Add vec_extract test cases.
    
    This patch adds test cases to verify that the vec_extract optimizations in
    include sign/zero extension with the load are generating code.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-char-1.c: New test.
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
            * gcc.target/powerpc/vec-extract-mem-short-1.c: New test.

Diff:
---
 .../gcc.target/powerpc/vec-extract-mem-char-1.c    | 22 +++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 37 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-extract-mem-short-1.c   | 37 ++++++++++++++++++++++
 3 files changed, 96 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..fa75c4c2a83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   QImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_0 (vector unsigned char *p)
+{
+  return vec_extract (*p, 0);		/* lbz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v16qi_1 (vector unsigned char *p)
+{
+  return vec_extract (*p, 1);		/* lbz, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e81ab4954ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+  return vec_extract (*p, 0);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+  return vec_extract (*p, 1);          /* lwa, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+  return vec_extract (*p, 0);          /* lwz, no rldicl.  */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+  return vec_extract (*p, 1);          /* lwz, no rldicl.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mextsw\M}   } } */
+/* { dg-final { scan-assembler-not   {\mrldicl\M}  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..19b7d879065
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   HImode and fold the sign/extension into the load.  */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+  return vec_extract (*p, 0);          /* lwa, no extsw.  */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+  return vec_extract (*p, 1);          /* lwa, no extsw.  */
+}
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+  return vec_extract (*p, 0);          /* lwz, no rlwinm.  */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+  return vec_extract (*p, 1);          /* lwz, no rlwinm.  */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M}    2 } } */
+/* { dg-final { scan-assembler-not   {\mextsh\M}    } } */
+/* { dg-final { scan-assembler-not   {\mrlwinm\M}   } } */

                 reply	other threads:[~2023-04-22  0:57 UTC|newest]

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