From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id B3B5F3857736; Sat, 22 Apr 2023 00:58:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3B5F3857736 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682125130; bh=g50ZxCe3g9dyoRDHcOZOp1/So+AZ90+xC+E0SuAoTFA=; h=From:To:Subject:Date:From; b=q7QHvlq+q4DiwobhjOlXbbV/ibYtS1+AZczZOzpn7bxSulrKaEipWVXia37HMU+le 32qcCttIBg4Vf0ZvgjmkMSMUghXSquZ+is2tK+mWKg7PT0NOt2vn0uNt6jGUfSlkzX nIn+LQlyy9o2gFro9h3nEBUrtQuOaOfmsuSVcyhQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: d0bc01e34e067428b4afa710ae92f00f63e272f9 X-Git-Newrev: 8ca5b658578bbfa9012f57884608b3bceb4124cd Message-Id: <20230422005850.B3B5F3857736@sourceware.org> Date: Sat, 22 Apr 2023 00:58:50 +0000 (GMT) List-Id: https://gcc.gnu.org/g:8ca5b658578bbfa9012f57884608b3bceb4124cd commit 8ca5b658578bbfa9012f57884608b3bceb4124cd Author: Michael Meissner Date: Fri Apr 21 20:58:46 2023 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 30b1619c5f2..0d54f525348 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,71 @@ +==================== Branch work119, patch #62 ==================== + +Add vec_extract test cases. + +This patch adds test cases to verify that the vec_extract optimizations in +include sign/zero extension with the load are generating code. + +2023-04-21 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-char-1.c: New test. + * gcc.target/powerpc/vec-extract-mem-int-1.c: New test. + * gcc.target/powerpc/vec-extract-mem-short-1.c: New test. + + +==================== Branch work119, patch #62 ==================== + +Fold V16QI vsx_extract from memory with constant element with zero extension. + +This patch folds V16QI vsx_extract from memory where the element number is +constant with zero extension to SImode/DImode. + +2023-04-21 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v16qi_load_to_u): New insn. + +==================== Branch work119, patch #62 ==================== + +Fold V8HI vsx_extract from memory with constant element with sign/zero extension. + +This patch folds V8HI vsx_extract from memory where the element number is +constant with sign or zero extension to SImode/DImode. + +2023-04-21 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v8hi_load_to_): New insn. + +==================== Branch work119, patch #62 ==================== + +Fold V4SI sign or zero extension into vsx_extract from memory with constant element. + +This patch folds V4SI vsx_extract from memory where the element number is +constant with sign or zero extension to DImode. + +2023-04-21 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4si_load_to_di): New insn. + +==================== Branch work119, patch #62 ==================== + +Allow integer vec_extract to load vector registers. + +2023-04-21 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute + (vsx_extract__load): Allow vec_extract of integer types with a + constant element number to load into vector registers. Don't require a + base register temporary if the element number is 0. + ==================== Branch work119, patch #61 ==================== Combine vec_extract of V4SF with DF convert with variable element.