From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A45CB3858C83; Sat, 22 Apr 2023 05:51:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A45CB3858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682142678; bh=Qm54NF1A6ZWZIkqVCBVF/l1GoFOzcToG79Gjm+QqA6I=; h=From:To:Subject:Date:From; b=uDJX2JfY29CuSe/QTZwOKeLJij/Qfn+uqOY3xcx6FzCBwZIRAPIv21KWPAQlqwyFw rmUetu+0EhN4lbfstoxxUU3d6cUVagTiKHTBcxpcj2Rx0fGHh6Ha1+YWVlpJcHHlS+ MC4F1VcYjqWbV/NQh1adX7shAXmVy9jCaQh6Xcjw= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers for variable element numbers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 87f139aae746c657c417d0fb34c425d335a8ead3 X-Git-Newrev: 97b99dca4bc0e0b3c5770a368f301c8c537a76b1 Message-Id: <20230422055118.A45CB3858C83@sourceware.org> Date: Sat, 22 Apr 2023 05:51:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:97b99dca4bc0e0b3c5770a368f301c8c537a76b1 commit 97b99dca4bc0e0b3c5770a368f301c8c537a76b1 Author: Michael Meissner Date: Sat Apr 22 01:51:01 2023 -0400 Allow integer vec_extract to load vector registers for variable element numbers. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load): Allow vec_extract of integer types with a constant element number to load into vector registers. Diff: --- gcc/config/rs6000/vsx.md | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 60f47d748a6..c49c323faeb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4083,12 +4083,12 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -4097,7 +4097,8 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,")]) ;; ISA 3.1 extract (define_expand "vextractl"