From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id BAEEA3858C50; Sat, 22 Apr 2023 06:02:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BAEEA3858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682143350; bh=NIPfnZMDibhSSum423Za3tTyQUjK69wRJxg/nVfWu9M=; h=From:To:Subject:Date:From; b=J86sJMQkLRvoiDtDhAmz83eR5lKlR5Hy8nfkcr65QISeDqbz7hcYKnK4sW36AzqvW 5b3HKo+70YNd4ZPZaFSykhkDeBE2quz1iBERhgDQzHOBWfKXxSuttbqcK1yyDz9iee XSfuVt8Ea1/J5PZ/bp+GVHZSIyBWD+ECH0RKLmo4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold V4SI sign or zero extension into vsx_extract from memory with variable element number. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 97b99dca4bc0e0b3c5770a368f301c8c537a76b1 X-Git-Newrev: ff7bc73e58e7127c65bd55239c868d2e01f359e5 Message-Id: <20230422060230.BAEEA3858C50@sourceware.org> Date: Sat, 22 Apr 2023 06:02:30 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ff7bc73e58e7127c65bd55239c868d2e01f359e5 commit ff7bc73e58e7127c65bd55239c868d2e01f359e5 Author: Michael Meissner Date: Sat Apr 22 02:02:09 2023 -0400 Fold V4SI sign or zero extension into vsx_extract from memory with variable element number. This patch folds V4SI vsx_extract from memory where the element number is variable with sign or zero extension to DImode. 2023-04-22 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_di): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c49c323faeb..5031801f71b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4100,6 +4100,27 @@ [(set_attr "type" "load,fpload") (set_attr "isa" "*,")]) +;; V4SI extract from memory with a variable element number converted to DImode +(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") + (any_extend:DI + (unspec:SI + [(match_operand:V4SI 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:DI (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SImode); +} + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,p8v")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand")