From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id B17A83858C83; Sat, 22 Apr 2023 06:08:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B17A83858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682143704; bh=xetRpbWuV5R3MV4uavgyPF6CzcJnCTqdfiVdur/MNF0=; h=From:To:Subject:Date:From; b=mD+qzLtH9iInkAXgNKm39XN+IX9yaJ/AjrG4AQnR4HjITuU93RLW9bOAfif+xrbOx toYr0NNf8zUNpKUIsBcUrEUnByPPhWVB7rkmkpQe+qyPeYpyHM8uh34OyveP7cxCss any1oI9EnHY4ZikCrxV+7IUYpkx0XWsKn8OEtuYM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold V8HI vsx_extract from memory with variable element with sign/zero extension. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: ff7bc73e58e7127c65bd55239c868d2e01f359e5 X-Git-Newrev: 20e689a11e7415ff9bfca4f098fdf20fd8d4bd0d Message-Id: <20230422060824.B17A83858C83@sourceware.org> Date: Sat, 22 Apr 2023 06:08:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:20e689a11e7415ff9bfca4f098fdf20fd8d4bd0d commit 20e689a11e7415ff9bfca4f098fdf20fd8d4bd0d Author: Michael Meissner Date: Sat Apr 22 02:08:07 2023 -0400 Fold V8HI vsx_extract from memory with variable element with sign/zero extension. This patch folds V8HI vsx_extract from memory where the element number is variable with sign or zero extension to SImode/DImode. 2023-04-22 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v8hi_load_to_): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 5031801f71b..5e27e4389b0 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4121,6 +4121,27 @@ [(set_attr "type" "load,fpload") (set_attr "isa" "*,p8v")]) +;; Extract a V8HI element from memory with a variable element number and sign +;; or zero extend it to either SImode or DImode. +(define_insn_and_split "*vsx_extract_v8hi_var_load_to_" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (any_extend:GPR + (unspec:SI + [(match_operand:V8HI 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], HImode); +} + [(set_attr "type" "load")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand")