From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3D15C3858C83; Sat, 22 Apr 2023 06:14:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3D15C3858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682144093; bh=HtzOE+JnoKxLtwDbdeDgRCxx7rdYbWcYkLooW75GsTA=; h=From:To:Subject:Date:From; b=GeYjO9JV7O5+LK6NnDOszONx+stE8PyiaTahX4/cIqhIJZjzl90gUPbC6eCc3ChLn 1FShx2SiJY08OAk0oax2QBfcuSuQ8zL+43BDCecdA7ndkmU8NxVr6bQBKZq+lSw9If NfU0U5YyBjdPDjqEdCF6KXj+dZD0O7j2KgJ//uLM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold V16QI vsx_extract from memory with variable element with zero extension. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 20e689a11e7415ff9bfca4f098fdf20fd8d4bd0d X-Git-Newrev: b964a3b6c113e35418f0e91c8408ea8f23b8c31a Message-Id: <20230422061453.3D15C3858C83@sourceware.org> Date: Sat, 22 Apr 2023 06:14:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b964a3b6c113e35418f0e91c8408ea8f23b8c31a commit b964a3b6c113e35418f0e91c8408ea8f23b8c31a Author: Michael Meissner Date: Sat Apr 22 02:14:35 2023 -0400 Fold V16QI vsx_extract from memory with variable element with zero extension. This patch folds V16QI vsx_extract from memory where the element number is variable with zero extension to SImode/DImode. 2023-04-21 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v16qi_load_to_u): New insn. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 5e27e4389b0..acda883564d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4142,6 +4142,27 @@ } [(set_attr "type" "load")]) +;; Extract a V16QI element from memory with a variable element number and zero +;; extend it to either SImode or DImode. +(define_insn_and_split "*vsx_extract_v16qi_var_load_to_u" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (zero_extend:GPR + (unspec:SI + [(match_operand:V16QI 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], QImode); +} + [(set_attr "type" "load")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand")