From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id 9393D385842C; Sun, 23 Apr 2023 13:41:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9393D385842C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682257262; bh=LOBIeD6Yf5cnW4S05TT/uLg+IkHsUDpOVINSiEXSy0U=; h=From:To:Subject:Date:From; b=cRofGfka6Xcd6LCX1G5MGr90lcoYIk1nnJ4T3eGkzvWTvXA0trMTuybe9jvLb0v4j S5aBitig3TfUDNKI7EdAHLQOX277opbAMJy3thW4GffRzP7ltfLkUHC0IwXRyvOvn8 vmt1Y0mzC/5Lc00ykLZIoR3dfIbCsTriN54eaVXU= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kyrylo Tkachov To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-178] aarch64: Add vect_concat with zeroes annotation to addp pattern X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/heads/master X-Git-Oldrev: 8ffff5e9de2fa8e2845c8045941afbb1e8638aed X-Git-Newrev: 3b13c59c835f92b353ef318398e39907cdeec4fa Message-Id: <20230423134102.9393D385842C@sourceware.org> Date: Sun, 23 Apr 2023 13:41:02 +0000 (GMT) List-Id: https://gcc.gnu.org/g:3b13c59c835f92b353ef318398e39907cdeec4fa commit r14-178-g3b13c59c835f92b353ef318398e39907cdeec4fa Author: Kyrylo Tkachov Date: Sun Apr 23 14:40:17 2023 +0100 aarch64: Add vect_concat with zeroes annotation to addp pattern Similar to others, the addp pattern can be safely annotated with to create the implicit vec_concat-with-zero variants. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_addp): Rename to... (aarch64_addp): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add testing for vpadd intrinsics. Diff: --- gcc/config/aarch64/aarch64-simd.md | 2 +- gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 17 +++++++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index adcad56cf55..4a1ec71995d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -6767,7 +6767,7 @@ ;; addp -(define_insn "aarch64_addp" +(define_insn "aarch64_addp" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w") diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 3ddd5a37af0..3fe0e53bcd0 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -37,13 +37,18 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5) FUNC (T, IS, OS, OP1, S) \ OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6) -OPSIX (int8, 8, 16, s8, add, sub, mul, and, orr, eor) -OPSIX (int16, 4, 8, s16, add, sub, mul, and, orr, eor) -OPSIX (int32, 2, 4, s32, add, sub, mul, and, orr, eor) +#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7) \ +FUNC (T, IS, OS, OP1, S) \ +OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7) + + +OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor) +OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor) +OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor) -OPSIX (uint8, 8, 16, u8, add, sub, mul, and, orr, eor) -OPSIX (uint16, 4, 8, u16, add, sub, mul, and, orr, eor) -OPSIX (uint32, 2, 4, u32, add, sub, mul, and, orr, eor) +OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor) +OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor) +OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor) /* { dg-final { scan-assembler-not {\tfmov\t} } } */ /* { dg-final { scan-assembler-not {\tmov\t} } } */