From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 141ED3858D1E; Mon, 24 Apr 2023 19:49:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 141ED3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682365775; bh=2S4WELZq+Ytkm6ZsYdNmtwpAhrxi2FUCPRc4ez1Ngwg=; h=From:To:Subject:Date:From; b=mYEzZoyWPQ2BJkwfUYzDEKBxXcvC3GY86D42RNPbH+/es2VHrP3iM8wenM1CM8hiZ asOmlxjBiGf09SDhhwthdKUpMCyFHIA/zyBQSa7fCbUHA8x4NNEPPeqVBam9nD31Aj OyCBk5UNJcpddhlwMy6x0q9rPvdSQbjIJgnz9HbQ= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Fold vsx_extract from memory with variable element to floating point. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: d6b9208d66fd2c1ae26394e6f918c19d83651491 X-Git-Newrev: f9ed17f6ef5359a5998ddce9a060032e63c1f430 Message-Id: <20230424194935.141ED3858D1E@sourceware.org> Date: Mon, 24 Apr 2023 19:49:35 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f9ed17f6ef5359a5998ddce9a060032e63c1f430 commit f9ed17f6ef5359a5998ddce9a060032e63c1f430 Author: Michael Meissner Date: Mon Apr 24 15:48:58 2023 -0400 Fold vsx_extract from memory with variable element to floating point. This patch folds V4SI/V8HI/V16QI vsx_extract from memory where the element number is variable and it is converted to floating point (both signed and unsigned floating point conversion). 2023-04-24 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load_to_u): New insn. (vsx_extract_v4si_var_load_to_s): New insn. (vsx_extract_v8hi_var_load_to_s): New insn. Diff: --- gcc/config/rs6000/vsx.md | 102 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f90005d4b63..ac8ae127055 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4269,6 +4269,108 @@ } [(set_attr "type" "load")]) +;; Extract a V4SI/V8HI/V16QI element from memory with a variable element number +;; and convert it to unsigned float. +(define_insn_and_split "*vsx_extract__var_load_to_u" + [(set (match_operand:FL_CONV 0 "register_operand" "=") + (unsigned_float:FL_CONV + (unspec: + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b")) + (clobber (match_scratch:DI 4 "="))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 4) + (zero_extend:DI (match_dup 5))) + (set (match_dup 0) + (float:FL_CONV (match_dup 4)))] +{ + machine_mode base_mode = mode; + + if (GET_CODE (operands[3]) == SCRATCH) + operands[3] = gen_reg_rtx (DImode); + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (DImode); + + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + base_mode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + +;; Extract a V4SI element from memory with a constant element number and +;; convert it to signed float. +(define_insn_and_split "*vsx_extract_v4si_var_load_to_s" + [(set (match_operand:FL_CONV 0 "register_operand" "=") + (float:FL_CONV + (unspec:SI + [(match_operand:V4SI 1 "memory_operand" "Q") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b")) + (clobber (match_scratch:DI 4 "="))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 4) + (sign_extend:DI (match_dup 5))) + (set (match_dup 0) + (float:FL_CONV (match_dup 4)))] +{ + if (GET_CODE (operands[3]) == SCRATCH) + operands[3] = gen_reg_rtx (DImode); + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (DImode); + + operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "fpload") + (set_attr "length" "8")]) + +;; Extract a V8HI element from memory with a constant element number and +;; convert it to signed float. While we could do this via a LXSIHZX +;; instruction followed by VEXTSB2D, it is better to do a LWA and MTVSRD +;; instruction. +(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" + [(set (match_operand:FL_CONV 0 "register_operand" "=") + (float:FL_CONV + (unspec:HI + [(match_operand:V8HI 1 "memory_operand" "Q") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b")) + (clobber (match_scratch:DI 4 "=&r")) + (clobber (match_scratch:DI 5 "="))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 4) + (sign_extend:DI (match_dup 6))) + (set (match_dup 5) + (match_dup 4)) + (set (match_dup 0) + (float:FL_CONV (match_dup 5)))] +{ + if (GET_CODE (operands[3]) == SCRATCH) + operands[3] = gen_reg_rtx (DImode); + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (DImode); + if (GET_CODE (operands[5]) == SCRATCH) + operands[5] = gen_reg_rtx (DImode); + + operands[6] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + HImode); +} + [(set_attr "type" "load") + (set_attr "length" "12")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand")