From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id DFA493858D32; Mon, 24 Apr 2023 22:57:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DFA493858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682377029; bh=7TjqQAvim5nHNEkDWTlKugsjrUVZw288Nu8h1AyvSIw=; h=From:To:Subject:Date:From; b=XkjW+4EUO6/WoeCS5OoGDTSCvgIy0xpW+C0x89JAmzdeq+JaMvcLYppA5SV+7eXto /EtnTVPdtSZ84OuMzD5nxLHEJecH3MUhie/mTldKWp0DuaBba818EFBk47x0dO5rbH Q43DjktGHnRUo7C7dURLgopfEoQcw/ZRG/pswqiI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: f9ed17f6ef5359a5998ddce9a060032e63c1f430 X-Git-Newrev: 2949dcf321ce4ba8ad6ac9d3a6e994b122d9c82b Message-Id: <20230424225709.DFA493858D32@sourceware.org> Date: Mon, 24 Apr 2023 22:57:09 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2949dcf321ce4ba8ad6ac9d3a6e994b122d9c82b commit 2949dcf321ce4ba8ad6ac9d3a6e994b122d9c82b Author: Michael Meissner Date: Mon Apr 24 18:57:06 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 362 +-------------------- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 22 -- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 37 --- .../gcc.target/powerpc/vec-extract-mem-short-1.c | 37 --- 4 files changed, 9 insertions(+), 449 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ac8ae127055..04877dd51f6 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,12 +223,6 @@ (V8HI "v") (V4SI "wa")]) -;; Mode attribute to give the isa constraint for accessing Altivec registers -;; with vector extract and insert operations. -(define_mode_attr VSX_EX_ISA [(V16QI "p9v") - (V8HI "p9v") - (V4SI "p8v")]) - ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -247,13 +241,6 @@ (TF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (TFmode)")]) -;; Mode attribute to give the constraint for floating point when used -;; with FL_CONV modes. -(define_mode_attr FL_CONV_REG [(SF "wa") - (DF "wa") - (KF "v") - (TF "v")]) - ;; Iterator for the 2 short vector types to do a splat from an integer (define_mode_iterator VSX_SPLAT_I [V16QI V8HI]) @@ -3984,15 +3971,13 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element -;; number. If the element number is 0, we don't need a temporary base -;; register. For vector registers, we require X-form addressing. +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r,r,,") + [(set (match_operand: 0 "register_operand" "=r") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q,Z,Q") - (parallel [(match_operand:QI 2 "" "O,n,O,n")]))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -4000,173 +3985,10 @@ { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "8") - (set_attr "isa" "*,*,,")]) - -;; Extract a V4SI element from memory with a constant element number and sign -;; or zero extend it to DImode. -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,Q,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,load,fpload,fpload") - (set_attr "length" "8")]) - -;; Extract a V8HI element from memory with a constant element number and sign -;; or zero extend it to either SImode or DImode. -(define_insn_and_split "*vsx_extract_v8hi_load_to_" - [(set (match_operand:GPR 0 "register_operand" "=r,r") - (any_extend:GPR - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,Q") - (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], HImode); } [(set_attr "type" "load") (set_attr "length" "8")]) -;; Extract a V16QI element from memory with a constant element number and -;; zero extend it to either SImode or DImode. -(define_insn_and_split "*vsx_extract_v16qi_load_to_u" - [(set (match_operand:GPR 0 "register_operand" "=r,r") - (zero_extend:GPR - (vec_select:QI - (match_operand:V16QI 1 "memory_operand" "m,Q") - (parallel [(match_operand:QI 2 "const_0_to_15_operand" "O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], QImode); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) - -;; Extract a V4SI/V8HI/V16QI element from memory with a constant element number -;; and convert it to unsigned float. -(define_insn_and_split "*vsx_extract__load_to_u" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (unsigned_float:FL_CONV - (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (parallel [(match_operand:QI 2 "const_int_operand" "n")])))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "="))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (zero_extend:DI (match_dup 5))) - (set (match_dup 0) - (float:FL_CONV (match_dup 4)))] -{ - machine_mode base_mode = mode; - - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - base_mode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8")]) - -;; Extract a V4SI element from memory with a constant element number and -;; convert it to signed float. -(define_insn_and_split "*vsx_extract_v4si_load_to_s" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (float:FL_CONV - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")])))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "="))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (sign_extend:DI (match_dup 5))) - (set (match_dup 0) - (float:FL_CONV (match_dup 4)))] -{ - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8")]) - -;; Extract a V8HI element from memory with a constant element number and -;; convert it to signed float. While we could do this via a LXSIHZX -;; instruction followed by VEXTSB2D, it is better to do a LWA and MTVSRD -;; instruction. -(define_insn_and_split "*vsx_extract_v8hi_load_to_s" - [(set (match_operand:FL_CONV 0 "register_operand" "=,") - (float:FL_CONV - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,Qo") - (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b")) - (clobber (match_scratch:DI 4 "=&r,&r")) - (clobber (match_scratch:DI 5 "=,"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (sign_extend:DI (match_dup 6))) - (set (match_dup 5) - (match_dup 4)) - (set (match_dup 0) - (float:FL_CONV (match_dup 5)))] -{ - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - if (GET_CODE (operands[5]) == SCRATCH) - operands[5] = gen_reg_rtx (DImode); - - operands[6] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load") - (set_attr "length" "12")]) - ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r") @@ -4189,12 +4011,12 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r,") + [(set (match_operand: 0 "gpc_reg_operand" "=r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b,&b"))] + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -4202,175 +4024,9 @@ { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], mode); -} - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,")]) - -;; V4SI extract from memory with a variable element number converted to DImode -(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") - (any_extend:DI - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SImode); -} - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,p8v")]) - -;; Extract a V8HI element from memory with a variable element number and sign -;; or zero extend it to either SImode or DImode. -(define_insn_and_split "*vsx_extract_v8hi_var_load_to_" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (any_extend:GPR - (unspec:SI - [(match_operand:V8HI 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], HImode); } [(set_attr "type" "load")]) -;; Extract a V16QI element from memory with a variable element number and zero -;; extend it to either SImode or DImode. -(define_insn_and_split "*vsx_extract_v16qi_var_load_to_u" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (zero_extend:GPR - (unspec:SI - [(match_operand:V16QI 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], QImode); -} - [(set_attr "type" "load")]) - -;; Extract a V4SI/V8HI/V16QI element from memory with a variable element number -;; and convert it to unsigned float. -(define_insn_and_split "*vsx_extract__var_load_to_u" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (unsigned_float:FL_CONV - (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:QI 2 "register_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "="))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (zero_extend:DI (match_dup 5))) - (set (match_dup 0) - (float:FL_CONV (match_dup 4)))] -{ - machine_mode base_mode = mode; - - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - base_mode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8")]) - -;; Extract a V4SI element from memory with a constant element number and -;; convert it to signed float. -(define_insn_and_split "*vsx_extract_v4si_var_load_to_s" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (float:FL_CONV - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q") - (match_operand:QI 2 "register_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "="))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (sign_extend:DI (match_dup 5))) - (set (match_dup 0) - (float:FL_CONV (match_dup 4)))] -{ - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8")]) - -;; Extract a V8HI element from memory with a constant element number and -;; convert it to signed float. While we could do this via a LXSIHZX -;; instruction followed by VEXTSB2D, it is better to do a LWA and MTVSRD -;; instruction. -(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" - [(set (match_operand:FL_CONV 0 "register_operand" "=") - (float:FL_CONV - (unspec:HI - [(match_operand:V8HI 1 "memory_operand" "Q") - (match_operand:DI 2 "register_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b")) - (clobber (match_scratch:DI 4 "=&r")) - (clobber (match_scratch:DI 5 "="))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (sign_extend:DI (match_dup 6))) - (set (match_dup 5) - (match_dup 4)) - (set (match_dup 0) - (float:FL_CONV (match_dup 5)))] -{ - if (GET_CODE (operands[3]) == SCRATCH) - operands[3] = gen_reg_rtx (DImode); - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - if (GET_CODE (operands[5]) == SCRATCH) - operands[5] = gen_reg_rtx (DImode); - - operands[6] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load") - (set_attr "length" "12")]) - ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index fa75c4c2a83..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,22 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold the sign/extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index e81ab4954ae..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index 19b7d879065..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold the sign/extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlha\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mlhz\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */