From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3E7433858D1E; Tue, 25 Apr 2023 01:54:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3E7433858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682387654; bh=wrjrRDkEQ1kRHINfTz17gCXjuzcJzdFsXgZAktqpvgY=; h=From:To:Subject:Date:From; b=SUon62ez9vq2Qp7Uw2DUlkvhEdAm4ysAgjB8vazg7xzNkp8JPXm0n5LD/FpN+42Z+ UNXSWDdxRRlxcLYq+Mu7xg1de1GFb99XuK8XbFlzX5j45g2rnfBMqdBXZt3gxmk1sq FzwmXPW8FZ1QVNRPr4o7qJI25Jz3luPzTZJH9WGU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 3f1c236b90f69acda6ba4dcabe07d60ff407a7f4 X-Git-Newrev: 51f1707cd47aeb16bd0a672210d1072dc0ebb362 Message-Id: <20230425015414.3E7433858D1E@sourceware.org> Date: Tue, 25 Apr 2023 01:54:14 +0000 (GMT) List-Id: https://gcc.gnu.org/g:51f1707cd47aeb16bd0a672210d1072dc0ebb362 commit 51f1707cd47aeb16bd0a672210d1072dc0ebb362 Author: Michael Meissner Date: Mon Apr 24 21:53:54 2023 -0400 Allow consant element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be loaded into vector registers directly. It also will be split before register allocation. This patch also adds support to rs6000_adjust_vec_address to allow it to be run before register allocation. 2023-04-24 Michael Meissner gcc/ * config/rs6000/rs6000.cc (get_vector_offset): Allow being called before register allocation. (adjust_vec_address_pcrel): Likewise. (rs6000_adjust_vec_address): Likewise. * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. (vsx_extract__load): Allow vector registers to be loaded. Diff: --- gcc/config/rs6000/rs6000.cc | 56 +++++++++++++++++++++++++++++++-------------- gcc/config/rs6000/vsx.md | 31 +++++++++++++++++-------- 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3be5860dd9b..65295dbaf81 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -7686,9 +7686,13 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (CONST_INT_P (element)) return GEN_INT (INTVAL (element) * scalar_size); - /* All insns should use the 'Q' constraint (address is a single register) if - the element number is not a constant. */ - gcc_assert (satisfies_constraint_Q (mem)); + if (GET_CODE (base_tmp) == SCRATCH) + base_tmp = gen_reg_rtx (Pmode); + + /* After register allocation, all insns should use the 'Q' constraint + (address is a single register) if the element number is not a + constant. */ + gcc_assert (can_create_pseudo_p () || satisfies_constraint_Q (mem)); /* Mask the element to make sure the element number is between 0 and the maximum number of elements - 1 so that we don't generate an address @@ -7704,6 +7708,9 @@ get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size) if (shift > 0) { rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift)); + if (can_create_pseudo_p ()) + base_tmp = gen_reg_rtx (Pmode); + emit_insn (gen_rtx_SET (base_tmp, shift_op)); } @@ -7747,6 +7754,9 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) else { + if (GET_CODE (base_tmp) == SCRATCH) + base_tmp = gen_reg_rtx (Pmode); + emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7769,9 +7779,8 @@ adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp) temporary (BASE_TMP) to fixup the address. Return the new memory address that is valid for reads or writes to a given register (SCALAR_REG). - This function is expected to be called after reload is completed when we are - splitting insns. The temporary BASE_TMP might be set multiple times with - this code. */ + The temporary BASE_TMP might be set multiple times with this code if this is + called after register allocation. */ rtx rs6000_adjust_vec_address (rtx scalar_reg, @@ -7784,8 +7793,11 @@ rs6000_adjust_vec_address (rtx scalar_reg, rtx addr = XEXP (mem, 0); rtx new_addr; - gcc_assert (!reg_mentioned_p (base_tmp, addr)); - gcc_assert (!reg_mentioned_p (base_tmp, element)); + if (GET_CODE (base_tmp) != SCRATCH) + { + gcc_assert (!reg_mentioned_p (base_tmp, addr)); + gcc_assert (!reg_mentioned_p (base_tmp, element)); + } /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); @@ -7841,6 +7853,9 @@ rs6000_adjust_vec_address (rtx scalar_reg, offset, it has the benefit that if D-FORM instructions are allowed, the offset is part of the memory access to the vector element. */ + if (GET_CODE (base_tmp) == SCRATCH) + base_tmp = gen_reg_rtx (Pmode); + emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1))); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } @@ -7848,26 +7863,33 @@ rs6000_adjust_vec_address (rtx scalar_reg, else { + if (GET_CODE (base_tmp) == SCRATCH) + base_tmp = gen_reg_rtx (Pmode); + emit_move_insn (base_tmp, addr); new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset); } - /* If the address isn't valid, move the address into the temporary base - register. Some reasons it could not be valid include: + /* If register allocation has been done and the address isn't valid, move + the address into the temporary base register. Some reasons it could not + be valid include: The address offset overflowed the 16 or 34 bit offset size; We need to use a DS-FORM load, and the bottom 2 bits are non-zero; We need to use a DQ-FORM load, and the bottom 4 bits are non-zero; Only X_FORM loads can be done, and the address is D_FORM. */ - enum insn_form iform - = address_to_insn_form (new_addr, scalar_mode, - reg_to_non_prefixed (scalar_reg, scalar_mode)); - - if (iform == INSN_FORM_BAD) + if (!can_create_pseudo_p ()) { - emit_move_insn (base_tmp, new_addr); - new_addr = base_tmp; + enum insn_form iform + = address_to_insn_form (new_addr, scalar_mode, + reg_to_non_prefixed (scalar_reg, scalar_mode)); + + if (iform == INSN_FORM_BAD) + { + emit_move_insn (base_tmp, new_addr); + new_addr = base_tmp; + } } return change_address (mem, scalar_mode, new_addr); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 04877dd51f6..0b7b26c2e2f 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3971,23 +3977,28 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element +;; number. If the element number is 0 or the address is offsettable, we don't +;; need a temporary base register. For vector registers, we require X-form +;; addressing. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=r,r,r,,") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,Q,Z,Q") + (parallel [(match_operand:QI 2 "" "O,n,n,O,n")]))) + (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,load,load,fpload,fpload") + (set_attr "length" "*,*,8,*,8") + (set_attr "isa" "*,*,*,,")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"