From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A3C2C3858D1E; Tue, 25 Apr 2023 01:58:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A3C2C3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682387932; bh=vZDaddEtr5KFEzu9+jUjt8JoH/eEg+EranK2SetaPPk=; h=From:To:Subject:Date:From; b=o+aEyD331Hkeh1LjD2DJkOVeCF2P5/caFpo95B35vL0csEOMeu9Fp1OUaCZUDKPiG E6PWLZXNw6ZzyY7++DLgPjdrV/sz/TOM+9x7bt6a3u5k4T1WdHhX2WOt4CbGlzYr3x UJ2Y/0Na50S6htI4gjhDW40ix/44ju87QJB2zIvo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 487a44be8605b917ff76a40f2ffdab94f5a52cde X-Git-Newrev: fb1b5a0868b45ff8d6dedc037c184f9822842900 Message-Id: <20230425015852.A3C2C3858D1E@sourceware.org> Date: Tue, 25 Apr 2023 01:58:52 +0000 (GMT) List-Id: https://gcc.gnu.org/g:fb1b5a0868b45ff8d6dedc037c184f9822842900 commit fb1b5a0868b45ff8d6dedc037c184f9822842900 Author: Michael Meissner Date: Mon Apr 24 21:58:48 2023 -0400 Revert patches Diff: --- gcc/ChangeLog.meissner | 46 +++++++++++++++ gcc/config/rs6000/vsx.md | 67 ---------------------- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 ----------- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 ----------- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 63 -------------------- .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 ----------- .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 ------------ 7 files changed, 46 insertions(+), 271 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index a31fb05b750..5210646122b 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,49 @@ +==================== Branch work119, patch #81 was reverted ==================== + +Allow consant element vec_extract to be zero or sign extended + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +constant element number to be zero extended. It also allows vec_extract of V4SI +and V8HI vector types with constant element number to be sign extended. + +2023-04-24 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4si_load_to_d): New insn. + (vsx_extract__load_to_u): New insn. + (vsx_extract_v8hi_load_to_z): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-char-1.c: New file. + * gcc.target/powerpc/vec-extract-mem-int-1.c: New file. + * gcc.target/powerpc/vec-extract-mem-int-2.c: New file. + * gcc.target/powerpc/vec-extract-mem-short-1.c: New file. + * gcc.target/powerpc/vec-extract-mem-short-2.c: New file. + +==================== Branch work119, patch #80 was reverted ==================== + +Allow consant element vec_extract to be loaded into vector registers. + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +constant element number to be loaded into vector registers directly. It also +will be split before register allocation. + +This patch also adds support to rs6000_adjust_vec_address to allow it to be run +before register allocation. + +2023-04-24 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (get_vector_offset): Allow being called before + register allocation. + (adjust_vec_address_pcrel): Likewise. + (rs6000_adjust_vec_address): Likewise. + * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. + (vsx_extract__load): Allow vector registers to be loaded. + ==================== Branch work119, patch #72 was reverted ==================== ==================== Branch work119, patch #71 was reverted ==================== diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a636a2a1470..0b7b26c2e2f 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4000,73 +4000,6 @@ (set_attr "length" "*,*,8,*,8") (set_attr "isa" "*,*,*,,")]) -;; Fold extracting a V4SI element with a constant element with either sign or -;; zero extension to DImode. -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8")]) - -;; Fold extracting a V8HI/V4SI element with a constant element with zero -;; extension to either DImode or SImode. -(define_insn_and_split "*vsx_extract__load_to_z" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v") - (zero_extend:GPR - (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8") - (set_attr "isa" "*,*,*,p9v,p9v")]) - -;; Fold extracting a V8HI element with a constant element with sign extension -;; to either DImode or SImode. -(define_insn_and_split "*vsx_extract_v8hi_load_to_z" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r") - (sign_extend:GPR - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,o,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load") - (set_attr "length" "*,*,8")]) - ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index 37cb9c0ae90..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_element_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index 3314f0cde3a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_0_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_3_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 3); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index 4d0e08908cc..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,63 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlwz\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ - -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlwz\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index f17bb874f01..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c deleted file mode 100644 index 47c41027a28..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_0_index_4 (vector short *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_3_index_4 (vector short *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlhz\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */