From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 44C233858D1E; Tue, 25 Apr 2023 02:11:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 44C233858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682388701; bh=KvefGd00wXqqCh31IRTcqUWOYMihqX6XaGBFTEeOPNM=; h=From:To:Subject:Date:From; b=kXoNIk5mPpO+TnqgV0Mix4aLJ8uDmKUliTSO1Q2lQyVqp9bMFfmpcuneaP+y8cB9H 8TBAfiuR85U23uvUEqbS1cNZdbq5T5ZipaT9ThI4MP//etP7zii69MbCT6Q/LdNkfF cLlnvvVy+BG13Vf1uhcpEL7E1BdWZAd4a4riFLgk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 62b7f25d96b490e5abf15c54e93bee3c1f87b65c X-Git-Newrev: 7f5887b68e9018ce346823aa06560ba99992a88e Message-Id: <20230425021141.44C233858D1E@sourceware.org> Date: Tue, 25 Apr 2023 02:11:41 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7f5887b68e9018ce346823aa06560ba99992a88e commit 7f5887b68e9018ce346823aa06560ba99992a88e Author: Michael Meissner Date: Mon Apr 24 22:11:21 2023 -0400 Allow variable element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a variable element number to be loaded into vector registers directly. It also will be split before register allocation. 2023-04-24 Michael Meissner gcc/ (vsx_extract__var_load): Allow vector registers to be loaded. Diff: --- gcc/config/rs6000/vsx.md | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 003bd534119..cc3bc83ff9b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4089,21 +4089,22 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,fpload")]) ;; ISA 3.1 extract (define_expand "vextractl"