From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 1D3D53858D1E; Tue, 25 Apr 2023 02:55:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1D3D53858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682391320; bh=0JhenDbd0EJekijRNqMcxxcU9HJuABrIAWaXfXpUL60=; h=From:To:Subject:Date:From; b=eFuejkkV3bjH4nYlqtaIjcNwO2sX3PJ1AaAN9x6Q4M8kX1HApBfCW46MvM74JToBR OsXcYE9Ejn+BsMWOI7sos7B21M6PIVh7ynY8f1a0zQ/62TGnjYFOrRcuf7E7jE1lRn 3CaIKLY9hORw38quShMSDBhIgv+WzrMbeFzlCH/4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 69f67cf89c8586efaab1e15aa78c4b983e702715 X-Git-Newrev: ade6286b050123ef8fcd9ff15e435bed8bd77e38 Message-Id: <20230425025520.1D3D53858D1E@sourceware.org> Date: Tue, 25 Apr 2023 02:55:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ade6286b050123ef8fcd9ff15e435bed8bd77e38 commit ade6286b050123ef8fcd9ff15e435bed8bd77e38 Author: Michael Meissner Date: Mon Apr 24 22:55:16 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 1fe1b591c74..3334848781f 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,40 @@ +==================== Branch work119, patch #83 ==================== + +Allow variable element vec_extract to be sign or zero extended + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +variable element number to be loaded with sign or zero extension, and GCC will +not generate a separate zero/sign extension instruction. + +2023-04-24 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_di): New insn. + (vsx_extract__var_load_to_u): New insn. + (vsx_extract_v8hi_var_load_to_s): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-int-3.c: New file. + * gcc.target/powerpc/vec-extract-mem-short-3.c: New file. + + +==================== Branch work119, patch #82 ==================== + +Allow variable element vec_extract to be loaded into vector registers. + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +variable element number to be loaded into vector registers directly. It also +will be split before register allocation. + +2023-04-24 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (vsx_extract__var_load): Allow vector + registers to be loaded. Split before register allocation. + ==================== Branch work119, patch #81 ==================== Allow consant element vec_extract to be zero or sign extended