[gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:a4af2c4c975dfe7e73ccaa1f942f80f404f6ec2f

commit a4af2c4c975dfe7e73ccaa1f942f80f404f6ec2f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 25 02:39:03 2023 -0400

    Allow variable element vec_extract to be sign or zero extended
    
    This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
    variable element number to be loaded with sign or zero extension, and GCC will
    not generate a separate zero/sign extension instruction.
    
    2023-04-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
            (vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
            (vsx_extract_v8hi_var_load_to_s<mode>): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
            * gcc.target/powerpc/vec-extract-mem-short-3.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
   [(set_attr "type" "load,fpload")
    (set_attr "isa" "*,<VSX_EX_ISA>")])
 
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+	(any_extend:DI
+	 (unspec:SI
+	  [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(any_extend:DI (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   SImode);
+}
+  [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+	(zero_extend:GPR
+	 (unspec:<VSX_EXTRACT_I2:MODE>
+	  [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+	   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extend:GPR (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   <VSX_EXTRACT_I2:MODE>mode);
+}
+  [(set_attr "type" "load,fpload")
+   (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+	(sign_extend:GPR
+	 (unspec:HI
+	  [(match_operand:V8HI 1 "memory_operand" "Q")
+	   (match_operand:DI 2 "gpc_reg_operand" "r")]
+	  UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(sign_extend:GPR (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+					   operands[2], operands[3],
+					   HImode);
+}
+  [(set_attr "type" "load")])
+
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")