From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id F258C3858404; Tue, 25 Apr 2023 13:55:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F258C3858404 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682430936; bh=kxpVVXNw/GulhDv465IrpBW66KxG07v7KLwGOgJiG1Q=; h=From:To:Subject:Date:From; b=Bc75S09qOaFMA733ZObWEew24FEM8vKFP6oyVWHKk/5NFszhV83khuiL/QmXX6HTs zuWPZ0cRBGBGlYzmeuqSQGVnHHy5Wp6A/zew91NOqWnFfYxEHGvZVDUhW6SdRHDWq2 OXAqWn4kKZGd1wXTTloKe9SyI5WsehJ+sGP47sdA= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kyrylo Tkachov To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-222] aarch64: PR target/PR99195 Annotate more simple integer binary patterns with vcz subst rules X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/heads/master X-Git-Oldrev: c69db3ef7f7d82a50f46038aa5457b7c8cc2d643 X-Git-Newrev: 9e9503e7b2c1517e8c46ea4d2e8805cc20301f34 Message-Id: <20230425135536.F258C3858404@sourceware.org> Date: Tue, 25 Apr 2023 13:55:36 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9e9503e7b2c1517e8c46ea4d2e8805cc20301f34 commit r14-222-g9e9503e7b2c1517e8c46ea4d2e8805cc20301f34 Author: Kyrylo Tkachov Date: Tue Apr 25 14:52:37 2023 +0100 aarch64: PR target/PR99195 Annotate more simple integer binary patterns with vcz subst rules This patch adds more straightforward annotations to some more integer binary ops to eliminate redundant fmovs around 64-bit SIMD results. Bootstrapped and tested on aarch64-none-linux. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (orn3): Rename to... (orn3): ... This. (bic3): Rename to... (bic3): ... This. (3): Rename to... (3): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for orn, bic, max and min. Diff: --- gcc/config/aarch64/aarch64-simd.md | 6 +++--- gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 19 +++++++++---------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5e1b4b18623..cb2223d29c2 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -423,7 +423,7 @@ (set_attr "length" "4")] ) -(define_insn "orn3" +(define_insn "orn3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) (match_operand:VDQ_I 2 "register_operand" "w")))] @@ -432,7 +432,7 @@ [(set_attr "type" "neon_logic")] ) -(define_insn "bic3" +(define_insn "bic3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) (match_operand:VDQ_I 2 "register_operand" "w")))] @@ -1671,7 +1671,7 @@ ) ;; Max/Min operations. -(define_insn "3" +(define_insn "3" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w") (match_operand:VDQ_BHSI 2 "register_operand" "w")))] diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 3fe0e53bcd0..5304e14b573 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -37,18 +37,17 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5) FUNC (T, IS, OS, OP1, S) \ OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6) -#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7) \ -FUNC (T, IS, OS, OP1, S) \ -OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7) - +#define OPELEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11) \ +OPFIVE (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5) \ +OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11) -OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor) -OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor) -OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor) +OPELEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor) -OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor) -OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor) +OPELEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) /* { dg-final { scan-assembler-not {\tfmov\t} } } */ /* { dg-final { scan-assembler-not {\tmov\t} } } */