From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 93D953858C2C; Wed, 26 Apr 2023 04:21:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 93D953858C2C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682482871; bh=0qU5HkGddRL4tsd1IZPJCE2idQkx3dAvUGvK6bvVNxU=; h=From:To:Subject:Date:From; b=Pv5JHdbo96d+Qq+7DTkXFmQR2SHVqWlcL6aLjvZprjf3EY/BBWsLub91P4gyC/TkQ Y+fQ/jmK9L8XtCCkhiBoTc2eWFq2gRc+Hxdi2+fD9DheLOZmd/jUzIDMOkxwdWWkMi PqpJeAbUrOXvmlwtrNJCUD5+x7oIIwLlWAK+AWsc= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-237] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: a010f0e08501b267ecb925ff88450f58e01dd991 X-Git-Newrev: 4f9eac2f262dfe938edf52045ef3fcdcf925af2d Message-Id: <20230426042111.93D953858C2C@sourceware.org> Date: Wed, 26 Apr 2023 04:21:11 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4f9eac2f262dfe938edf52045ef3fcdcf925af2d commit r14-237-g4f9eac2f262dfe938edf52045ef3fcdcf925af2d Author: Ju-Zhe Zhong Date: Wed Mar 22 20:15:56 2023 +0800 RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen Current expansion of vmsge will make RA produce redundant vmv1r.v. testcase: void f1 (void * in, void *out, int32_t x) { vbool32_t mask = *(vbool32_t*)in; asm volatile ("":::"memory"); vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4); vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v, x, 4); m4 = __riscv_vmsge_vv_i32m1_b32_m (m4, v2, v2, 4); __riscv_vsm_v_b32 (out, m4, 4); } Before this patch: f1: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v0,0(a0) vsetivli zero,4,e32,m1,ta,mu vle32.v v3,0(a0) vle32.v v2,0(a0),v0.t vmslt.vx v1,v3,a2 vmnot.m v1,v1 vmslt.vx v1,v3,a2,v0.t vmxor.mm v1,v1,v0 vmv1r.v v0,v1 vmsge.vv v2,v2,v2,v0.t vsm.v v2,0(a1) ret After this patch: f1: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v0,0(a0) vsetivli zero,4,e32,m1,ta,mu vle32.v v3,0(a0) vle32.v v2,0(a0),v0.t vmslt.vx v1,v3,a2 vmnot.m v1,v1 vmslt.vx v1,v3,a2,v0.t vmxor.mm v0,v1,v0 vmsge.vv v2,v2,v2,v0.t vsm.v v2,0(a1) ret gcc/ChangeLog: * config/riscv/vector.md: Fix redundant vmv1r.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-150.c: Adapt assembly check. Diff: --- gcc/config/riscv/vector.md | 15 +++++++-------- .../gcc.target/riscv/rvv/base/binop_vx_constraint-150.c | 2 +- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a8d8721f95a..413d9744d6b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4141,6 +4141,7 @@ { enum rtx_code code = GET_CODE (operands[3]); rtx undef = RVV_VUNDEF (mode); + rtx tmp = gen_reg_rtx (mode); if (code == GEU && rtx_equal_p (operands[5], const0_rtx)) { /* If vmsgeu with 0 immediate, expand it to vmset. */ @@ -4187,12 +4188,11 @@ - pseudoinstruction: vmsge{u}.vx vd, va, x - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */ emit_insn ( - gen_pred_cmp_scalar (operands[0], operands[1], operands[2], + gen_pred_cmp_scalar (tmp, operands[1], operands[2], operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn (gen_pred_nand (operands[0], CONSTM1_RTX (mode), - undef, operands[0], operands[0], - operands[6], operands[8])); + undef, tmp, tmp, operands[6], operands[8])); } else { @@ -4201,13 +4201,12 @@ /* masked va >= x, vd == v0 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */ - rtx reg = gen_reg_rtx (mode); emit_insn (gen_pred_cmp_scalar ( - reg, CONSTM1_RTX (mode), undef, operands[3], operands[4], + tmp, CONSTM1_RTX (mode), undef, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn ( gen_pred_andnot (operands[0], CONSTM1_RTX (mode), undef, - operands[1], reg, operands[6], operands[8])); + operands[1], tmp, operands[6], operands[8])); } else { @@ -4216,10 +4215,10 @@ - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0. */ emit_insn (gen_pred_cmp_scalar ( - operands[0], operands[1], operands[2], operands[3], operands[4], + tmp, operands[1], operands[2], operands[3], operands[4], operands[5], operands[6], operands[7], operands[8])); emit_insn (gen_pred (XOR, mode, operands[0], - CONSTM1_RTX (mode), undef, operands[0], + CONSTM1_RTX (mode), undef, tmp, operands[1], operands[6], operands[8])); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c index 55a222f47ea..e92a8115f09 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c @@ -18,4 +18,4 @@ void f1 (void * in, void *out, int32_t x) /* { dg-final { scan-assembler-times {vmslt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {vmv} 1 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */