From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D9D3E3858D1E; Wed, 26 Apr 2023 15:37:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9D3E3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682523444; bh=Uq7fHo8UV72P4N48U7bwXyfYbjlrhDE9ngD2daG+kqo=; h=From:To:Subject:Date:From; b=HmYNdx55mG6nxnSzrbWXz5X9gaLHqPOezrgde9LwnphhEB2bIKC5LEC6GFs/VcX5y +vTE0bLR56vJzoF7qwXHVRppneCZEBgIEDwgtT/ztIswAQX4WkE3PzQdP3w5LB+ZNF GLfnpDbXUcGIFfgQPyvadWALZDeyXRzE3LrC3zzM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 5a759794517862efcfa7ac6a5b18afdb6e16bd5e X-Git-Newrev: 31dd0a8cefcf602ef2d4ceaad30bcdb8ebbd2a90 Message-Id: <20230426153724.D9D3E3858D1E@sourceware.org> Date: Wed, 26 Apr 2023 15:37:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:31dd0a8cefcf602ef2d4ceaad30bcdb8ebbd2a90 commit 31dd0a8cefcf602ef2d4ceaad30bcdb8ebbd2a90 Author: Michael Meissner Date: Wed Apr 26 11:37:21 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 85 ++-------------------- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 --------- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 --------- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 36 --------- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 0 .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 --------- .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 --------- .../gcc.target/powerpc/vec-extract-mem-short-3.c | 0 8 files changed, 8 insertions(+), 254 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 497aac24319..0b7b26c2e2f 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4000,73 +4000,6 @@ (set_attr "length" "*,*,8,*,8") (set_attr "isa" "*,*,*,,")]) -;; Fold extracting a V4SI element with a constant element with either sign or -;; zero extension to DImode. -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8")]) - -;; Fold extracting a V8HI/V4SI element with a constant element with zero -;; extension to either DImode or SImode. -(define_insn_and_split "*vsx_extract__load_to_u" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v") - (zero_extend:GPR - (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8") - (set_attr "isa" "*,*,*,p9v,p9v")]) - -;; Fold extracting a V8HI element with a constant element with sign extension -;; to either DImode or SImode. -(define_insn_and_split "*vsx_extract_v8hi_load_to_s" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r") - (sign_extend:GPR - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,o,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load") - (set_attr "length" "*,*,8")]) - ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r") @@ -4089,23 +4022,21 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r,") + [(set (match_operand: 0 "gpc_reg_operand" "=r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b,&b"))] + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); } - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,")]) + [(set_attr "type" "load")]) ;; ISA 3.1 extract (define_expand "vextractl" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index 046a203cebc..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_element_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index 6341a59433c..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_0_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_3_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 3); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index f86935e51d2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index e1cf0c91048..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c deleted file mode 100644 index 43e889acb5c..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_0_index_4 (vector short *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_3_index_4 (vector short *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c new file mode 100644 index 00000000000..e69de29bb2d