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From: Patrick O'Neill <poneill@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-280] RISC-V: Fix sync.md and riscv.cc whitespace errors Date: Wed, 26 Apr 2023 23:07:49 +0000 (GMT) [thread overview] Message-ID: <20230426230749.D63D93858D3C@sourceware.org> (raw) https://gcc.gnu.org/g:2a26872984c109a98d0ad733b0c68c3e1648ec86 commit r14-280-g2a26872984c109a98d0ad733b0c68c3e1648ec86 Author: Patrick O'Neill <patrick@rivosinc.com> Date: Wed Apr 26 14:13:19 2023 -0700 RISC-V: Fix sync.md and riscv.cc whitespace errors This patch fixes whitespace errors introduced with https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html 2023-04-26 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv.cc: Fix whitespace. * config/riscv/sync.md: Fix whitespace. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Diff: --- gcc/config/riscv/riscv.cc | 6 +++--- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0f890469d7a..1529855a2b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, gen_lowpart (QImode, *shift))); - emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); + emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); } /* Leftshift a subword within an SImode register. */ @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, mode, 0)); - emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, - gen_lowpart (QImode, shift))); + emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, + gen_lowpart (QImode, shift))); } /* Initialize the GCC target structure. */ diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 83be6431cb6..19274528262 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -128,10 +128,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -193,10 +193,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -367,7 +367,7 @@ { rtx difference = gen_rtx_MINUS (SImode, val, exp); compare = gen_reg_rtx (SImode); - emit_move_insn (compare, difference); + emit_move_insn (compare, difference); } if (word_mode != SImode) @@ -393,10 +393,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong<mode> to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -461,7 +461,7 @@ "TARGET_ATOMIC" { /* We have no QImode atomics, so use the address LSBs to form a mask, - then use an aligned SImode atomic. */ + then use an aligned SImode atomic. */ rtx result = operands[0]; rtx mem = operands[1]; rtx model = operands[2];
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