From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 6DF173858D20; Thu, 27 Apr 2023 02:48:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6DF173858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682563700; bh=hfWYH7GGvrKy1zaOdsfWhskD0EBBScwbY0z0vc0AlDA=; h=From:To:Subject:Date:From; b=pZ7mYlKpzAzxHaWNbA6/VvgI9R14BFYED4AFC9tFS/2Bj2b8Lya7b/PBj6jcNTOUC 3+ucNUsUBHW0LvCsw+2JK39RQ62NaSeI8E4/HQ7gUdiV/OQjXyVhRMjm5tNUxdu0rd PKFAwqaAy8eNAnAdq8WvCiow8WDWFu5zqy27+CWk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: fd4678813d4e738ac876fed4eaa4ecd51c854568 X-Git-Newrev: f3b776659ca12b3f13091fb506f480ebb96e1b8d Message-Id: <20230427024820.6DF173858D20@sourceware.org> Date: Thu, 27 Apr 2023 02:48:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f3b776659ca12b3f13091fb506f480ebb96e1b8d commit f3b776659ca12b3f13091fb506f480ebb96e1b8d Author: Michael Meissner Date: Wed Apr 26 22:48:16 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/rs6000.md | 3 - gcc/config/rs6000/vsx.md | 122 --------------------- .../gcc.target/powerpc/vec-extract-mem-char-2.c | 40 ------- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 31 ------ .../gcc.target/powerpc/vec-extract-mem-int-4.c | 40 ------- .../gcc.target/powerpc/vec-extract-mem-int-5.c | 40 ------- .../gcc.target/powerpc/vec-extract-mem-short-3.c | 19 ---- .../gcc.target/powerpc/vec-extract-mem-short-4.c | 40 ------- 8 files changed, 335 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b1e3750f528..7d6c94aee5b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -664,9 +664,6 @@ (float "") (unsigned_float "uns")]) -(define_code_attr fp_int_extend [(float "sign_extend") - (unsigned_float "zero_extend")]) - ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. (define_mode_attr wd [(QI "b") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index bbc049dc44f..497aac24319 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4045,62 +4045,6 @@ (set_attr "length" "*,*,8,*,8") (set_attr "isa" "*,*,*,p9v,p9v")]) -;; Fold extracting a V4SI element with a constant element with either sign or -;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID. -(define_insn_and_split "*vsx_extract_v4si_load_to_" - [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") - (any_float:SFDF - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b")) - (clobber (match_scratch:DI 4 "=wa,wa"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 4) - (:DI (match_dup 5))) - (set (match_dup 0) - (float:SFDF (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8,12")]) - -;; Fold extracting a V8HI/V16QI element with a constant element with zero -;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID -(define_insn_and_split "*vsx_extract__load_to_uns" - [(set (match_operand:SFDF 0 "register_operand" "=wa,wa") - (unsigned_float:SFDF - (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n")])))) - (clobber (match_scratch:DI 3 "=X,&b")) - (clobber (match_scratch:DI 4 "=v,v"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_P9_VECTOR" - "#" - "&& 1" - [(set (match_dup 4) - (zero_extend:DI (match_dup 5))) - (set (match_dup 0) - (float:SFDF (match_dup 4)))] -{ - if (GET_CODE (operands[4]) == SCRATCH) - operands[4] = gen_reg_rtx (DImode); - - operands[5] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8,12")]) - ;; Fold extracting a V8HI element with a constant element with sign extension ;; to either DImode or SImode. (define_insn_and_split "*vsx_extract_v8hi_load_to_s" @@ -4163,72 +4107,6 @@ [(set_attr "type" "load,fpload") (set_attr "isa" "*,")]) -;; Variable V4SI extract from memory with sign or zero conversion to DImode. -(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") - (any_extend:DI - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "load,fpload")]) - -;; Variable V8HI/V16QI extract from memory with zero conversion to either -;; SImode or DImode. -(define_insn_and_split "*vsx_extract__var_load_to_u" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v") - (zero_extend:GPR - (unspec: - [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,p9v")]) - -;; Variable V8HI extract from memory with sign conversion to either -;; SImode or DImode. -(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (sign_extend:GPR - (unspec:HI - [(match_operand:V8HI 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load")]) - ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c deleted file mode 100644 index fd6b6d03699..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and convert it to unsigned floating point, by loading the value - directly to a vector register, rather than loading up a GPR and transfering - the result to a vector register.. */ - -#include - -double -extract_dbl_uns_v16qi_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */ -} - -double -extract_dbl_uns_v16qi_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */ -} - -float -extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */ -} - -float -extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */ -} - -/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */ -/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */ -/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c index f6b027db3bc..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c @@ -1,31 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - SImode and fold both zero and sign extension into the load. Both uses - generate a rldicl to clear the bits in the variable element number, but this - test verifies that there is no rldicl after the lwzx to do the zero - extension. */ - -#include -#include - -long long -extract_sign_v4si_var (vector int *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -unsigned long long -extract_uns_v4si_var (vector unsigned int *p, size_t n) -{ - return vec_extract (*p, n); /* lwzx, no extra rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ -/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c deleted file mode 100644 index 79f634b33b0..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and convert it to unsigned floating point, by loading the value - directly to a vector register, rather than loading up a GPR and transfering - the result to a vector register.. */ - -#include - -double -extract_dbl_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ -} - -double -extract_dbl_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ -} - -float -extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ -} - -float -extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ -} - -/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c deleted file mode 100644 index d51d26482c3..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and convert it to signed floating point, by loading the value - directly to a vector register, rather than loading up a GPR and transfering - the result to a vector register.. */ - -#include - -double -extract_dbl_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ -} - -double -extract_dbl_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */ -} - -float -extract_flt_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ -} - -float -extract_flt_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */ -} - -/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsr} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c index a1d3947fabb..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c @@ -1,19 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - HImode and fold sign extension into the load. */ - -#include -#include - -long long -extract_sign_v8hi_var (vector short *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -/* { dg-final { scan-assembler {\mlhax\M} } } */ -/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c deleted file mode 100644 index 24ad6fd3a7e..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c +++ /dev/null @@ -1,40 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and convert it to unsigned floating point, by loading the value - directly to a vector register, rather than loading up a GPR and transfering - the result to a vector register.. */ - -#include - -double -extract_dbl_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */ -} - -double -extract_dbl_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */ -} - -float -extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */ -} - -float -extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */ -} - -/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */ -/* { dg-final { scan-assembler-not {\mmtvsr} } } */