From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 9D6853858D20; Thu, 27 Apr 2023 02:51:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9D6853858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682563880; bh=0dVr7YgW5Jizi97/Jkx7cy4H1J70HxsVunWMffHy4XU=; h=From:To:Subject:Date:From; b=srOItsmKUlVGvG0+RfdqTbuPGVsM31zd96bRaQngQUgxTSSJjJB5tXh5Ovcn5S7TZ M/Kb0aCdOrq7cBD5DJbLzAtv1LycOYewCLYEYL3JpjeRU8Syu8kVYIvYTXMys1o8x/ P1aDgvGK5/85uK8BGYXx9FFa5COW8JN9+VSSy3Rk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: f3b776659ca12b3f13091fb506f480ebb96e1b8d X-Git-Newrev: 740252409e56eb3c22b9c336ba524f442cc2c4e2 Message-Id: <20230427025120.9D6853858D20@sourceware.org> Date: Thu, 27 Apr 2023 02:51:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:740252409e56eb3c22b9c336ba524f442cc2c4e2 commit 740252409e56eb3c22b9c336ba524f442cc2c4e2 Author: Michael Meissner Date: Wed Apr 26 22:51:16 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 497aac24319..003bd534119 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4089,23 +4089,21 @@ ;; Variable V16QI/V8HI/V4SI extract from memory (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r,") + [(set (match_operand: 0 "gpc_reg_operand" "=r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b,&b"))] + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); } - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,")]) + [(set_attr "type" "load")]) ;; ISA 3.1 extract (define_expand "vextractl"