From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id EA4653858D20; Thu, 27 Apr 2023 02:58:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA4653858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682564325; bh=nycf6ACuYWJLKerTT2q/nHat5TxOYRnMhfUL7hKK2U8=; h=From:To:Subject:Date:From; b=ITx1FzpTO57ZXhFvbTo/a7lcrOdmK/KIWMfoieLltNGb1Wmip6btLjFsJS3je9smg iuUUgh6+RYSLE7Uk0tbeUF2J+H8boGO8JKs0pu83iyLeytbqweWZS2npvimoPGGU90 INekSM6HMCGc47Ntg3kusoev4/zVMJUBqPj5EaHU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: a18459b28378eacf5e1c73d5f88d942b34b7cbef X-Git-Newrev: 1aae4cc74b48ec33740548412ef4c3e9f57ba855 Message-Id: <20230427025845.EA4653858D20@sourceware.org> Date: Thu, 27 Apr 2023 02:58:45 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1aae4cc74b48ec33740548412ef4c3e9f57ba855 commit 1aae4cc74b48ec33740548412ef4c3e9f57ba855 Author: Michael Meissner Date: Wed Apr 26 22:58:42 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 66 ---------------------- .../gcc.target/powerpc/vec-extract-mem-int-3.c | 31 ---------- .../gcc.target/powerpc/vec-extract-mem-short-3.c | 19 ------- 3 files changed, 116 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 62f9702554a..19a502b99a3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4110,72 +4110,6 @@ [(set_attr "type" "load,fpload") (set_attr "isa" "*,")]) -;; Variable V4SI extract from memory with sign or zero conversion to DImode. -(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") - (any_extend:DI - (unspec:SI - [(match_operand:V4SI 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "load,fpload")]) - -;; Variable V8HI/V16QI extract from memory with zero conversion to either -;; SImode or DImode. -(define_insn_and_split "*vsx_extract__var_load_to_u" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v") - (zero_extend:GPR - (unspec: - [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q") - (match_operand:DI 2 "gpc_reg_operand" "r,r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "load,fpload") - (set_attr "isa" "*,p9v")]) - -;; Variable V8HI extract from memory with sign conversion to either -;; SImode or DImode. -(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (sign_extend:GPR - (unspec:HI - [(match_operand:V8HI 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (sign_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load")]) - ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c index f6b027db3bc..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c @@ -1,31 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - SImode and fold both zero and sign extension into the load. Both uses - generate a rldicl to clear the bits in the variable element number, but this - test verifies that there is no rldicl after the lwzx to do the zero - extension. */ - -#include -#include - -long long -extract_sign_v4si_var (vector int *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -unsigned long long -extract_uns_v4si_var (vector unsigned int *p, size_t n) -{ - return vec_extract (*p, n); /* lwzx, no extra rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ -/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c index a1d3947fabb..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c @@ -1,19 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mvsx" } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ - -/* Test to verify that the vec_extract with variable element numbers can load - HImode and fold sign extension into the load. */ - -#include -#include - -long long -extract_sign_v8hi_var (vector short *p, size_t n) -{ - return vec_extract (*p, n); /* lwax, no extsw. */ -} - -/* { dg-final { scan-assembler {\mlhax\M} } } */ -/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */