From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1461) id 1B5D03858D32; Thu, 27 Apr 2023 09:32:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B5D03858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682587928; bh=tmgrYjnshi3cWMEE3ZIcb4Zq5iurds/rKVXbUOkYFMo=; h=From:To:Subject:Date:From; b=RssdC131vf9d4qpMj9AjXsNVXuTiGPT/KiyhNptS2zaK68DmppvMpzCpaZAe+Cfxf PXcTuTjLXvYv1nAew3Zzc86TtlMddO0NjYR4VHFl98/bZ4oUKMosio9XbHdzicgZDK TY4War1s6P6gs/6ojUagGVssBqrP+pqtPbIGXUEI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Andrew Stubbs To: gcc-cvs@gcc.gnu.org Subject: [gcc/devel/omp/gcc-12] amdgcn: Fix addsub bug X-Act-Checkin: gcc X-Git-Author: Andrew Stubbs X-Git-Refname: refs/heads/devel/omp/gcc-12 X-Git-Oldrev: fe884508f6b92ae84ba888b1fc431327ed0b2388 X-Git-Newrev: a410f603fcaf2b963af5607eb359907fe273426e Message-Id: <20230427093208.1B5D03858D32@sourceware.org> Date: Thu, 27 Apr 2023 09:32:08 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a410f603fcaf2b963af5607eb359907fe273426e commit a410f603fcaf2b963af5607eb359907fe273426e Author: Andrew Stubbs Date: Wed Apr 26 15:23:48 2023 +0100 amdgcn: Fix addsub bug The vec_fmsubadd instuction actually had add twice, by mistake. Also improve code-gen for all the complex patterns by using properly undefined values. Mostly this just prevents the compiler reserving space in the stack frame. gcc/ChangeLog: * config/gcn/gcn-valu.md (cmul3): Use gcn_gen_undef. (cml4): Likewise. (vec_addsub3): Likewise. (cadd3): Likewise. (vec_fmaddsub4): Likewise. (vec_fmsubadd4): Likewise, and use sub for the odd lanes. Diff: --- gcc/ChangeLog.omp | 9 +++++++++ gcc/config/gcn/gcn-valu.md | 23 +++++++++++++++-------- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index 72948e409f8..c8a12d10884 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -1,3 +1,12 @@ +2023-04-27 Andrew Stubbs + + * config/gcn/gcn-valu.md (cmul3): Use gcn_gen_undef. + (cml4): Likewise. + (vec_addsub3): Likewise. + (cadd3): Likewise. + (vec_fmaddsub4): Likewise. + (vec_fmsubadd4): Likewise, and use sub for the odd lanes. + 2023-04-21 Andrew Stubbs Backport from mainline: diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index ae532d9d3d8..a6380f91f5c 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2382,8 +2382,9 @@ rtx even = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (even, get_exec (0x5555555555555555UL)); rtx dest = operands[0]; - emit_insn (gen_3_exec (dest, t1, t1_perm, dest, even)); - // a*c-b*d 0 + emit_insn (gen_3_exec (dest, t1, t1_perm, + gcn_gen_undef (mode), + even)); // a*c-b*d 0 rtx t2_perm = gen_reg_rtx (mode); emit_insn (gen_dpp_swap_pairs (t2_perm, t2)); // b*c a*d @@ -2427,7 +2428,8 @@ rtx even = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (even, get_exec (0x5555555555555555UL)); rtx dest = operands[0]; - emit_insn (gen_sub3_exec (dest, t1, t2_perm, dest, even)); + emit_insn (gen_sub3_exec (dest, t1, t2_perm, + gcn_gen_undef (mode), even)); rtx odd = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (odd, get_exec (0xaaaaaaaaaaaaaaaaUL)); @@ -2451,7 +2453,8 @@ rtx dest = operands[0]; rtx x = operands[1]; rtx y = operands[2]; - emit_insn (gen_sub3_exec (dest, x, y, dest, even)); + emit_insn (gen_sub3_exec (dest, x, y, gcn_gen_undef (mode), + even)); rtx odd = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (odd, get_exec (0xaaaaaaaaaaaaaaaaUL)); emit_insn (gen_add3_exec (dest, x, y, dest, odd)); @@ -2478,7 +2481,9 @@ rtx even = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (even, get_exec (0x5555555555555555UL)); - emit_insn (gen_3_exec (dest, x, y, dest, even)); + emit_insn (gen_3_exec (dest, x, y, + gcn_gen_undef (mode), + even)); rtx odd = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (odd, get_exec (0xaaaaaaaaaaaaaaaaUL)); emit_insn (gen_3_exec (dest, x, y, dest, odd)); @@ -2498,7 +2503,8 @@ rtx even = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (even, get_exec (0x5555555555555555UL)); rtx dest = operands[0]; - emit_insn (gen_sub3_exec (dest, t1, operands[3], dest, even)); + emit_insn (gen_sub3_exec (dest, t1, operands[3], + gcn_gen_undef (mode), even)); rtx odd = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (odd, get_exec (0xaaaaaaaaaaaaaaaaUL)); emit_insn (gen_add3_exec (dest, t1, operands[3], dest, odd)); @@ -2518,10 +2524,11 @@ rtx even = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (even, get_exec (0x5555555555555555UL)); rtx dest = operands[0]; - emit_insn (gen_add3_exec (dest, t1, operands[3], dest, even)); + emit_insn (gen_add3_exec (dest, t1, operands[3], + gcn_gen_undef (mode), even)); rtx odd = gen_rtx_REG (DImode, EXEC_REG); emit_move_insn (odd, get_exec (0xaaaaaaaaaaaaaaaaUL)); - emit_insn (gen_add3_exec (dest, t1, operands[3], dest, odd)); + emit_insn (gen_sub3_exec (dest, t1, operands[3], dest, odd)); DONE; })