From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D4A0E3858D37; Thu, 27 Apr 2023 20:50:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D4A0E3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682628644; bh=yKARLO0K7pPMs1PjD3H3BjVj29maQmkJfVabq5aBSKg=; h=From:To:Subject:Date:From; b=nCp+tV5JsBKDAjnGQND+mmjpEu0SU0SancocfUFSJhFfC/kkVwXG4qJrZzWqP3JM+ IbdwvoTDOU5ns49rQlgCXmOYwl9Fc22g1J00aUw5GAW7D4zbwlI14KQNiS71RjQdJX qzcu9etM6DRL4kuHxgpcOstOZQr68Y8aWRHp04pA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 9d4c959c2bf6ff9f2eb8834d1652bdddc2519e66 X-Git-Newrev: dceb9d2a8859af37f420abd2272880952d54a35c Message-Id: <20230427205044.D4A0E3858D37@sourceware.org> Date: Thu, 27 Apr 2023 20:50:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:dceb9d2a8859af37f420abd2272880952d54a35c commit dceb9d2a8859af37f420abd2272880952d54a35c Author: Michael Meissner Date: Thu Apr 27 16:50:41 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 49 ++-------------------- .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 ------------- 2 files changed, 4 insertions(+), 74 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 3a4b8cdb02a..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3549,7 +3549,6 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory with constant element number. (define_insn_and_split "*vsx_extract_v4sf_load" [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF @@ -3558,7 +3557,7 @@ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], @@ -3566,28 +3565,7 @@ } [(set_attr "type" "fpload,fpload,fpload,load") (set_attr "length" "8") - (set_attr "isa" "*,p8v,p9v,*")]) - -;; V4SF extract from memory with constant element number and convert to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" "=f,v,v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,Z,m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))) - (clobber (match_scratch:P 3 "=&b,&b,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& 1" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "8") - (set_attr "isa" "*,p8v,p9v")]) + (set_attr "isa" "*,p7v,p9v,*")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" @@ -3607,7 +3585,7 @@ DONE; }) -;; V4SF extract from memory with variable element number. +;; Variable V4SF extract from memory (define_insn_and_split "*vsx_extract_v4sf_var_load" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r") (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q") @@ -3616,7 +3594,7 @@ (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], @@ -3624,25 +3602,6 @@ } [(set_attr "type" "fpload,load")]) -;; V4SF extract from memory with variable element number and convert to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& 1" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload")]) - ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index 4670e261ba8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include - -void -extract_v4sf_gpr_0 (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -void -extract_v4sf_gpr_1 (vector float *p, float *q) -{ - float x = vec_extract (*p, 1); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */