From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id A4A763858CDA; Fri, 28 Apr 2023 03:44:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4A763858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682653484; bh=NkzewbhuGj+BkEz4wFKv9n+8+52pZiLyqefh5ELtgII=; h=From:To:Subject:Date:From; b=QSwIbrxdoCH1H7tl5koL4c4VlaJOI0vOPMF4JEoRdGka2+12zoraKgKtWImAdLZ4s FAvAZ3tYk/YL4fPRNxI+7+wCJwOvuT8+mlZevVTNB/YpyACaVXBWNVtFgrO20ZVzHo 6ICbVM2pDZRz05c4puJTGRmtVP1Igbyl6VaZOvQU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 0e7d826ea61b3b964a8ed88ea835a2dc74dc6aab X-Git-Newrev: 254a02cd8df1afb9393c2526473d9254debdebcd Message-Id: <20230428034444.A4A763858CDA@sourceware.org> Date: Fri, 28 Apr 2023 03:44:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:254a02cd8df1afb9393c2526473d9254debdebcd commit 254a02cd8df1afb9393c2526473d9254debdebcd Author: Michael Meissner Date: Thu Apr 27 23:44:41 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index b82c649fdf6..514c593ada8 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,33 @@ +==================== Branch work119, patch #97 ==================== + +Allow constant element vec_extract to be converted to floating point + +This patch allows vec_extract of the following types to be converted to +floating point by loading the value directly to the vector register, and then +doing the conversion instead of loading the value to a GPR and then doing a +direct move: + + vector int + vector unsigned int + vector unsigned short + vector unsigned char + +2023-04-27 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.md (fp_int_extend): New code attribute. + * config/rs6000/vsx.md (vsx_extract_v4si_load_to_): New + * insn. + * vsx_extract__load_to_uns: New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-char-2.c: New file. + * gcc.target/powerpc/vec-extract-mem-int-4.c: New file. + * gcc.target/powerpc/vec-extract-mem-int_5.c: New file. + * gcc.target/powerpc/vec-extract-mem-short-4.c: New file. + ==================== Branch work119, patch #96 ==================== Allow variable element vec_extract to be sign or zero extended @@ -19,7 +49,6 @@ gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-int-3.c: New file. * gcc.target/powerpc/vec-extract-mem-short-3.c: New file. - ==================== Branch work119, patch #95 ==================== Allow variable element vec_extract to be loaded into vector registers.