From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1666) id 357503858425; Fri, 28 Apr 2023 11:36:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 357503858425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682681809; bh=5kKPI+RBf2V1TUBDf1f0Lm9z5OZTw9gjACw5j5NKo0I=; h=From:To:Subject:Date:From; b=aYGY9e1OzaNPpNFazG0HmoyC3FGinJBipqi8j4xt0klIhOcvpg6yPZk95AV7MaXQE N3cyTERWK47cJlE/Jf18nUBpAT0fQ4ScKl5l5wRH+lGOd0NXAq9wAjw7ndOKfKHnoD ChEBLILSX1/rQ3vrykAotriZlPZY1PlGrDWPhqK0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Biener To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-326] ipa/109652 - ICE in modification phase of IPA SRA X-Act-Checkin: gcc X-Git-Author: Richard Biener X-Git-Refname: refs/heads/master X-Git-Oldrev: cacf65d74463600815773255e8b82b4043432bd7 X-Git-Newrev: a94dcac59ee4c99b523ae593cb1c0ad43d4a110b Message-Id: <20230428113649.357503858425@sourceware.org> Date: Fri, 28 Apr 2023 11:36:49 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a94dcac59ee4c99b523ae593cb1c0ad43d4a110b commit r14-326-ga94dcac59ee4c99b523ae593cb1c0ad43d4a110b Author: Richard Biener Date: Fri Apr 28 08:40:07 2023 +0200 ipa/109652 - ICE in modification phase of IPA SRA There's another questionable IL transform by IPA SRA, replacing foo (p_1(D)->x) with foo (VIEW_CONVERT (ISRA.PARM.1)) where ISRA.PARM.1 is a register. Conversion of a register to an aggregate type is questionable but not entirely unreasonable and not within the set of IL I am rejecting when fixing PR109644. The following lets this slip through in IPA SRA transform by restricting re-gimplification to the case of register type results. To not break the previous testcase again we need to optimize the BIT_FIELD_REF , ...> case to elide the conversion. PR ipa/109652 * ipa-param-manipulation.cc (ipa_param_body_adjustments::modify_expression): Allow conversion of a register to a non-register type. Elide conversions inside BIT_FIELD_REFs. * gcc.dg/torture/pr109652.c: New testcase. Diff: --- gcc/ipa-param-manipulation.cc | 7 ++++-- gcc/testsuite/gcc.dg/torture/pr109652.c | 40 +++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/gcc/ipa-param-manipulation.cc b/gcc/ipa-param-manipulation.cc index 33dcab9c33c..a286af7f5d9 100644 --- a/gcc/ipa-param-manipulation.cc +++ b/gcc/ipa-param-manipulation.cc @@ -1836,9 +1836,11 @@ ipa_param_body_adjustments::modify_expression (tree *expr_p, bool convert, || TREE_CODE (expr) == IMAGPART_EXPR || TREE_CODE (expr) == REALPART_EXPR) { + /* For a BIT_FIELD_REF do not bother to VIEW_CONVERT the base, + instead reference the replacement directly. */ + convert = TREE_CODE (expr) != BIT_FIELD_REF; expr_p = &TREE_OPERAND (expr, 0); expr = *expr_p; - convert = true; } ipa_param_body_replacement *pbr = get_expr_replacement (expr, false); @@ -1861,7 +1863,8 @@ ipa_param_body_adjustments::modify_expression (tree *expr_p, bool convert, gcc_checking_assert (tree_to_shwi (TYPE_SIZE (TREE_TYPE (expr))) == tree_to_shwi (TYPE_SIZE (TREE_TYPE (repl)))); tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (expr), repl); - if (is_gimple_reg (repl)) + if (is_gimple_reg (repl) + && is_gimple_reg_type (TREE_TYPE (expr))) { gcc_assert (extra_stmts); vce = force_gimple_operand (vce, extra_stmts, true, NULL_TREE); diff --git a/gcc/testsuite/gcc.dg/torture/pr109652.c b/gcc/testsuite/gcc.dg/torture/pr109652.c new file mode 100644 index 00000000000..8a6524d2212 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr109652.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ + +typedef int UInt; +UInt skeletal_RI5_instr; +__attribute__((__noreturn__)) void vex_assert_fail(); +typedef struct { + union { + struct { + UInt imm5; + } I5; + } ARMri5; +} ARMRI5; +typedef enum { ARMin_Alu, ARMin_Shift } ARMInstrTag; +void iregEnc(); +static UInt skeletal_RI5(ARMRI5 *ri) { + UInt imm5 = ri->ARMri5.I5.imm5; + __builtin_expect(imm5, 1) ?: vex_assert_fail(); + iregEnc(ri->ARMri5); + return skeletal_RI5_instr; +} +ARMInstrTag emit_ARMInstr_i_0; +void *emit_ARMInstr_disp_cp_chain_me_to_slowEP() { + switch (emit_ARMInstr_i_0) { + case ARMin_Alu: + UInt instr, subopc; + UInt rD, rN; + goto bad; + instr |= subopc | rN; + case ARMin_Shift: + rD = 0; + UInt rM = 0; + ARMRI5 argR; + instr = skeletal_RI5(&argR); + instr |= rD | rM; + goto done; + } +bad: +done: + return 0; +}