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From: Jeff Law <law@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-340] RISC-V: Eliminate redundant zero extension of minu/maxu operands Date: Fri, 28 Apr 2023 15:11:11 +0000 (GMT) [thread overview] Message-ID: <20230428151111.A13D83858D37@sourceware.org> (raw) https://gcc.gnu.org/g:1966741378d5f456d0245960fa09074b6320b4d6 commit r14-340-g1966741378d5f456d0245960fa09074b6320b4d6 Author: Jivan Hakobyan <jivanhakobyan9@gmail.com> Date: Fri Apr 28 09:09:45 2023 -0600 RISC-V: Eliminate redundant zero extension of minu/maxu operands RV64 the following code: unsigned Min(unsigned a, unsigned b) { return a < b ? a : b; } Compiles to: Min: zext.w a1,a1 zext.w a0,a0 minu a0,a1,a0 sext.w a0,a0 ret This patch removes unnecessary zero extensions of minu/maxu operands. gcc/ChangeLog: * config/riscv/bitmanip.md: Added expanders for minu/maxu instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-min-max-02.c: Updated scanning check. * gcc.target/riscv/zbb-min-max-03.c: New tests. Diff: --- gcc/config/riscv/bitmanip.md | 25 ++++++++++++++++++++++++- gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c | 4 ++-- gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c | 13 +++++++++++++ 3 files changed, 39 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index c21247aa3fa..6617876bb0b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -401,7 +401,30 @@ DONE; }) -(define_insn "<bitmanip_optab><mode>3" +(define_expand "<bitmanip_optab>di3" + [(set (match_operand:DI 0 "register_operand" "=r") + (bitmanip_minmax:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBB") + +(define_expand "<bitmanip_optab>si3" + [(set (match_operand:SI 0 "register_operand" "=r") + (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ZBB" +{ + if (TARGET_64BIT) + { + rtx t = gen_reg_rtx (DImode); + operands[1] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[1])); + operands[2] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[2])); + emit_insn (gen_<bitmanip_optab>di3 (t, operands[1], operands[2])); + emit_move_insn (operands[0], gen_lowpart (SImode, t)); + DONE; + } +}) + +(define_insn "*<bitmanip_optab><mode>3" [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") (match_operand:X 2 "reg_or_0_operand" "rJ")))] diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c index b462859f10f..edfbf807d45 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ int f(unsigned int* a) { @@ -9,6 +9,6 @@ int f(unsigned int* a) } /* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-times "sext.w" 1 } } */ +/* { dg-final { scan-assembler-not "sext.w" } } */ /* { dg-final { scan-assembler-not "zext.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c index c7de1004048..38c932b9580 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c @@ -6,5 +6,18 @@ int f(int x) { return x >= 0 ? x : 0; } +unsigned f2(unsigned x, unsigned y) { + return x > y ? x : y; +} + +unsigned f3(unsigned x, unsigned y) { + return x < y ? x : y; +} + /* { dg-final { scan-assembler-times "max\t" 1 } } */ /* { dg-final { scan-assembler-not "li\t" } } */ +/* { dg-final { scan-assembler-times "maxu\t" 1 } } */ +/* { dg-final { scan-assembler-times "minu\t" 1 } } */ +/* { dg-final { scan-assembler-not "zext.w" } } */ +/* { dg-final { scan-assembler-not "sext.w" } } */ +
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