From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id B41473857731; Fri, 28 Apr 2023 18:08:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B41473857731 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682705305; bh=nzWQmFwE8D+If6rUDph1OyWDk6801WyRekaXVQurDiw=; h=From:To:Subject:Date:From; b=tIntSW8PbsMhPLYfhQO3HxIu8tEJTSNBnDm7RgR1ePi7/SS3a29dIz+f3/FBqQpoN AJnMzmnrZY27lbQfOQJdJrJoppK3ngSvtnPGB4GdEnSwb20tgsNnEcSR6A2VuQKq5l ikL7k8TiQ4e33gb30FKGoHLrkky+wZOlX4znQMg4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 6ae84406009ffdb652e64382d9b2646c54859c5e X-Git-Newrev: ab2977bdf39f57e12321b53c1dcb3fc3e1b1a5fa Message-Id: <20230428180825.B41473857731@sourceware.org> Date: Fri, 28 Apr 2023 18:08:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ab2977bdf39f57e12321b53c1dcb3fc3e1b1a5fa commit ab2977bdf39f57e12321b53c1dcb3fc3e1b1a5fa Author: Michael Meissner Date: Fri Apr 28 14:08:08 2023 -0400 Allow consant element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be loaded into vector registers directly. It also will be split before register allocation. In doing so, I restricted the optimization to only occur if the memory address did not use an Altivec style address with AND -16. 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. (vsx_extract__load): Allow vector registers to be loaded. Do insn split before register allocation. Restrict vector addresses to not use Altivec addressing. Diff: --- gcc/config/rs6000/vsx.md | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 42336bbf36b..ecf1279c95b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3971,23 +3977,26 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element +;; number. For vector registers, we require X-form addressing. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=r,") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q") + (parallel [(match_operand:QI 2 "" "n,n")]))) + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,fpload") + (set_attr "length" "8") + (set_attr "isa" "*,")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"