From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E0A353858D37; Fri, 28 Apr 2023 18:25:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E0A353858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682706339; bh=6vsOB2I0wm+pAHT6nU0gYOcSTOH9prl0/imJ6c7WqMY=; h=From:To:Subject:Date:From; b=LAoetk5/K10WAJjI4j9nICrE2je9FT5wJ36KhynNeGZGoJhW957zUj/bB0ybBGwj0 r7TQPRHIO14flRkUCP2rN23kqas7YR4b3pPzF3LzUB7vIPIirKy6UUNvMa1MWuX8oO bXPlM1dKVg8WiHS1xQIaSvpQktJZ4rWQGCcoWZBs= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 1d27b30b506a528a4872e27956a22dc2d50418a7 X-Git-Newrev: adf1281cb08bd1548419e9290b7bc5f1eed4f799 Message-Id: <20230428182539.E0A353858D37@sourceware.org> Date: Fri, 28 Apr 2023 18:25:39 +0000 (GMT) List-Id: https://gcc.gnu.org/g:adf1281cb08bd1548419e9290b7bc5f1eed4f799 commit adf1281cb08bd1548419e9290b7bc5f1eed4f799 Author: Michael Meissner Date: Fri Apr 28 14:25:18 2023 -0400 Allow variable element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a variable element number to be loaded into vector registers directly. It also will be split before register allocation. In doing so, I restricted the optimization to only occur if the memory address did not use an Altivec style address with AND -16. 2023-04-27 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract__var_load): Allow vector registers to be loaded. Split before register allocation. Restrict vector addresses to not use Altivec addressing. Diff: --- gcc/config/rs6000/vsx.md | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index feb7fc753a6..dc8d45d30e7 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4085,23 +4085,28 @@ } [(set_attr "isa" "p9v,*")]) -;; Variable V16QI/V8HI/V4SI extract from memory +;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload +;; on power8 due to the vector byte swap support which creates Altivec +;; addresses. These are eliminated after register allocation since we use 'Q' +;; or 'Z' constraints. (define_insn_and_split "*vsx_extract__var_load" - [(set (match_operand: 0 "gpc_reg_operand" "=r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] + [(match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=&b"))] + (clobber (match_scratch:DI 3 "=&b,&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load")]) + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,")]) ;; ISA 3.1 extract (define_expand "vextractl"