From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 1B06D3857357; Fri, 28 Apr 2023 18:36:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B06D3857357 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682707009; bh=6prN6le7F2og1sE5SnXcZGAndZsdVAL+03ie+sSJrz8=; h=From:To:Subject:Date:From; b=NkiZUUgGoPIVfVvSJHrkA+oIQaRfKUn6q2r5ViyBVqbyYn8eim4gAtmGXzpXS2rsk wtKkKrb31VU8g+KPYddqjl8gFlQCOsM+9cn1JGZWt/6fiOH3q+ZLU5LXt3Lzoc/Rhh CTii6J4E7+ShsE1KXU5V95hEOZ5AVhISoiIRVNgE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: ae852218fb682cc99389da854dda9efbf9457360 X-Git-Newrev: 8a92aa10770cfc06fbf36e32f163df9967803030 Message-Id: <20230428183649.1B06D3857357@sourceware.org> Date: Fri, 28 Apr 2023 18:36:49 +0000 (GMT) List-Id: https://gcc.gnu.org/g:8a92aa10770cfc06fbf36e32f163df9967803030 commit 8a92aa10770cfc06fbf36e32f163df9967803030 Author: Michael Meissner Date: Fri Apr 28 14:36:17 2023 -0400 Allow variable element vec_extract to be sign or zero extended This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a variable element number to be loaded with sign or zero extension, and GCC will not generate a separate zero/sign extension instruction. 2023-04-27 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_di): New insn. (vsx_extract__var_load_to_u): New insn. (vsx_extract_v8hi_var_load_to_s): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-int-3.c: New file. * gcc.target/powerpc/vec-extract-mem-short-3.c: New file. Diff: --- gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-3.c | 31 ++++++++++ .../gcc.target/powerpc/vec-extract-mem-short-3.c | 19 +++++++ 3 files changed, 116 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 9d98b962f66..e33675781ce 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4108,6 +4108,72 @@ [(set_attr "type" "load,fpload") (set_attr "isa" "*,")]) +;; Variable V4SI extract from memory with sign or zero conversion to DImode. +(define_insn_and_split "*vsx_extract_v4si_var_load_to_di" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa") + (any_extend:DI + (unspec:SI + [(match_operand:V4SI 1 "non_altivec_memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 0) + (any_extend:DI (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "load,fpload")]) + +;; Variable V8HI/V16QI extract from memory with zero conversion to either +;; SImode or DImode. +(define_insn_and_split "*vsx_extract__var_load_to_u" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v") + (zero_extend:GPR + (unspec: + [(match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 0) + (zero_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); +} + [(set_attr "type" "load,fpload") + (set_attr "isa" "*,p9v")]) + +;; Variable V8HI extract from memory with sign conversion to either +;; SImode or DImode. +(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (sign_extend:GPR + (unspec:HI + [(match_operand:V8HI 1 "non_altivec_memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& 1" + [(set (match_dup 0) + (sign_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + HImode); +} + [(set_attr "type" "load")]) + ;; ISA 3.1 extract (define_expand "vextractl" [(set (match_operand:V2DI 0 "altivec_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c index e69de29bb2d..f6b027db3bc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Test to verify that the vec_extract with variable element numbers can load + SImode and fold both zero and sign extension into the load. Both uses + generate a rldicl to clear the bits in the variable element number, but this + test verifies that there is no rldicl after the lwzx to do the zero + extension. */ + +#include +#include + +long long +extract_sign_v4si_var (vector int *p, size_t n) +{ + return vec_extract (*p, n); /* lwax, no extsw. */ +} + +unsigned long long +extract_uns_v4si_var (vector unsigned int *p, size_t n) +{ + return vec_extract (*p, n); /* lwzx, no extra rldicl. */ +} + +/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */ +/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */ +/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c index e69de29bb2d..a1d3947fabb 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Test to verify that the vec_extract with variable element numbers can load + HImode and fold sign extension into the load. */ + +#include +#include + +long long +extract_sign_v8hi_var (vector short *p, size_t n) +{ + return vec_extract (*p, n); /* lwax, no extsw. */ +} + +/* { dg-final { scan-assembler {\mlhax\M} } } */ +/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */ +/* { dg-final { scan-assembler-not {\mextsh\M} } } */