From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 8CD633858D37; Fri, 28 Apr 2023 22:56:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8CD633858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682722560; bh=o/8oNJNkGM5CISONSDFN9vzk9goMu1+p21d0HsSsKdo=; h=From:To:Subject:Date:From; b=FkaGu9lW+UQCQoz3Ba134Z9XLpe4ucLuzI146HKDTq4Yv2pfOmeNw9KmQudNPk7fO xQNJTa7WBCkzEy1bhByusQS/u3P6alGrYEstRbIjpZBLGLDQhFr5ytFJmR8EGMHEWp v2rFI74163dhl5PY+TmiUcGPEdDANveo+eAxa/Gs= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 0939f74cd682d703c4e799c3a33a3f76633ce5da X-Git-Newrev: 1941eb946d423b0ffffb66eef1d94377a559d94c Message-Id: <20230428225600.8CD633858D37@sourceware.org> Date: Fri, 28 Apr 2023 22:56:00 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1941eb946d423b0ffffb66eef1d94377a559d94c commit 1941eb946d423b0ffffb66eef1d94377a559d94c Author: Michael Meissner Date: Fri Apr 28 18:55:39 2023 -0400 Allow consant element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be loaded into vector registers directly. This patch also adds support for optimzing 0 element number to not need a base register tempoary. Likewise, if we have an offsettable address, we don't need to allocate a scratch register. 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. (vsx_extract__load): Allow vector registers to be loaded. Add optimizations for loading up element 0 and/or with an offsettable address. Diff: --- gcc/config/rs6000/vsx.md | 84 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 +++++++++ .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 +++++++++ .../gcc.target/powerpc/vec-extract-mem-int-2.c | 36 ++++++++++ .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 +++++++++ .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 ++++++++++ 6 files changed, 261 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 73b1e8896fd..f25b29855f4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4023,6 +4023,90 @@ (set_attr "length" "4,4,8,4,8") (set_attr "isa" "*,*,*,,")]) +;; Fold extracting a V4SI element with a constant element with either sign or +;; zero extension to DImode. +;; Alternatives: +;; 1: GPR, element 0, normal address, no modification +;; 2: GPR, element 0-3, offsettable address +;; 3: GPR, element 0-3, single register (offset to op[3]) +;; 4: VSX, element 0, X-form address, no modification +;; 5: VSX, element 0-3, single register (offset to op[3]) +(define_insn_and_split "*vsx_extract_v4si_load_to_di" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa") + (any_extend:DI + (vec_select:SI + (match_operand:V4SI 1 "memory_operand" "m,o,m,Z,Q") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")])))) + (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (any_extend:DI (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + SImode); +} + [(set_attr "type" "load,load,load,fpload,fpload") + (set_attr "length" "*,*,8,*,8")]) + +;; Fold extracting a V8HI/V4SI element with a constant element with zero +;; extension to either DImode or SImode. +;; Alternatives: +;; 1: GPR, element 0, normal address, no modification +;; 2: GPR, element 0-3, offsettable address +;; 3: GPR, element 0-3, single register (offset to op[3]) +;; 4: VMX, element 0, X-form address, no modification +;; 5: VMX, element 0-3, single register (offset to op[3]) +(define_insn_and_split "*vsx_extract__load_to_u" + [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v") + (zero_extend:GPR + (vec_select: + (match_operand:VSX_EXTRACT_I2 1 "memory_operand" + "m,o,m,Z,Q") + (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")])))) + (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); +} + [(set_attr "type" "load,load,load,fpload,fpload") + (set_attr "length" "*,*,8,*,8") + (set_attr "isa" "*,*,*,p9v,p9v")]) + +;; Fold extracting a V8HI element with a constant element with sign extension +;; to either DImode or SImode. +;; Alternatives: +;; 1: GPR, element 0, normal address, no modification +;; 2: GPR, element 0-3, offsettable address +;; 3: GPR, element 0-3, single register (offset to op[3]) +(define_insn_and_split "*vsx_extract_v8hi_load_to_s" + [(set (match_operand:GPR 0 "register_operand" "=r,r,r") + (sign_extend:GPR + (vec_select:HI + (match_operand:V8HI 1 "memory_operand" "m,o,m") + (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")])))) + (clobber (match_scratch:DI 3 "=X,X,&b"))] + "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (sign_extend:GPR (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + HImode); +} + [(set_attr "type" "load") + (set_attr "length" "8")]) + ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c new file mode 100644 index 00000000000..61f021ee99f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + QImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v16qi_element_0 (vector unsigned char *p) +{ + return vec_extract (*p, 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_1 (vector unsigned char *p) +{ + return vec_extract (*p, 1); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 3); /* lbz, no rlwinm. */ +} + +/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c new file mode 100644 index 00000000000..e59ceae6866 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v4si_0 (vector unsigned int *p) +{ + return vec_extract (*p, 0); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_1 (vector unsigned int *p) +{ + return vec_extract (*p, 1); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_element_0_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 0); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_element_3_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 3); /* lwz, no rldicl. */ +} + +/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c new file mode 100644 index 00000000000..052371e72ef --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold sign extension into the load. */ + +#include + +long long +extract_sign_v4si_0 (vector int *p) +{ + return vec_extract (*p, 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_1 (vector int *p) +{ + return vec_extract (*p, 1); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_element_0_index_4 (vector int *p) +{ + return vec_extract (p[4], 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_element_3_index_4 (vector int *p) +{ + return vec_extract (p[4], 3); /* lwa, no extsw. */ +} + +/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */ +/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c new file mode 100644 index 00000000000..65ae21b1a1c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v8hi_0 (vector unsigned short *p) +{ + return vec_extract (*p, 0); /* lwz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_1 (vector unsigned short *p) +{ + return vec_extract (*p, 1); /* lwz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 3); /* lbz, no rlwinm. */ +} + +/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c new file mode 100644 index 00000000000..6a2f23cfc57 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + HImode and fold sign extension into the load. */ + +#include + +long long +extract_sign_v8hi_0 (vector short *p) +{ + return vec_extract (*p, 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_1 (vector short *p) +{ + return vec_extract (*p, 1); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_element_0_index_4 (vector short *p) +{ + return vec_extract (p[4], 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_element_3_index_4 (vector short *p) +{ + return vec_extract (p[4], 3); /* lwa, no extsw. */ +} + +/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */ +/* { dg-final { scan-assembler-not {\mextsh\M} } } */