From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 6D2A93858D37; Fri, 28 Apr 2023 22:57:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D2A93858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682722634; bh=Fi323zCwJIR2EfEFtaUBueT4AsZK+gsJ+4TD94+Jt7Y=; h=From:To:Subject:Date:From; b=awniadz5bBYyglYQoQkV63A9/2KRjS2oeeRBasvV4qAGI22Da7ZIg6KpRK9QJ3iAe Ywo1Dkc7bk/lJLlOYunzt5UAPf8seGpyuDlABrGin28KB1jOcRmYb2zV6VEtFpUa7Q BM1BR+qClaObcYtvrl6NNpvrXea+mqv2gV8UOGvM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 1941eb946d423b0ffffb66eef1d94377a559d94c X-Git-Newrev: 37ab1b98ce5aafc0e8bc2a2dd2478f1f560ee96f Message-Id: <20230428225714.6D2A93858D37@sourceware.org> Date: Fri, 28 Apr 2023 22:57:14 +0000 (GMT) List-Id: https://gcc.gnu.org/g:37ab1b98ce5aafc0e8bc2a2dd2478f1f560ee96f commit 37ab1b98ce5aafc0e8bc2a2dd2478f1f560ee96f Author: Michael Meissner Date: Fri Apr 28 18:57:10 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 156 +-------------------- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 ----- .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 ---- .../gcc.target/powerpc/vec-extract-mem-float-2.c | 22 --- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 ----- .../gcc.target/powerpc/vec-extract-mem-int-2.c | 36 ----- .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 ----- .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 ----- 8 files changed, 7 insertions(+), 377 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f25b29855f4..7121f50a449 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3555,22 +3555,12 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory with constant element number. -;; Alternatives: -;; 1: Load FPR, index 0, normal address, no address change. -;; 2: Load FPR, index 0-3, offsettable address, element folded into addr. -;; 3: Load FPR, index 0-3, single register, offset in op[3]. -;; 4: Load VMX, index 0, x-form, power8, no address change. -;; 5: Load VMX, index 0-3, single register, power8, offset in op[3]. -;; 6: Load VMX, index 0, normal address, power9, no address change. -;; 7: Load VMX, index 0-3, offsettable address, power9, element in addr. -;; 8: Load GPR, index 0-3, single register, offset in op[3]. (define_insn_and_split "*vsx_extract_v4sf_load" - [(set (match_operand:SF 0 "register_operand" "=f,f,f,v,v,v,v,?r") + [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,o,Q,Z,Q,m,o,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n,O,n,n")]))) - (clobber (match_scratch:P 3 "=X,X,&b,X,&b,X,X,&b"))] + (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) + (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" "&& reload_completed" @@ -3579,38 +3569,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" "fpload,fpload,fpload,fpload,fpload,fpload,fpload,load") - (set_attr "length" "4,4,8,4,8,4,4,8") - (set_attr "isa" "*,*,*,p8v,p8v,p9v,p9v,*")]) - -;; V4SF extract from memory with constant element number and convert to DFmode. -;; Alternatives: -;; 1: Load FPR, index 0, normal address, no address change. -;; 2: Load FPR, index 0-3, offsettable address, element folded into addr. -;; 3: Load FPR, index 0-3, single register, offset in op[3]. -;; 4: Load VMX, index 0, x-form, power8, no address change. -;; 5: Load VMX, index 0-3, single register, power8, offset in op[3]. -;; 6: Load VMX, index 0, normal address, power9, no address change. -;; 7: Load VMX, index 0-3, offsettable address, power9, element in addr. -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" "=f,f,f,v,v,v,v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,o,Q,Z,Q,m,o") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n,O,n")])))) - (clobber (match_scratch:P 3 "=X,X,&b,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload") - (set_attr "length" "4,4,8,4,8,4,4") - (set_attr "isa" "*,*,*,p8v,p8v,p9v,p9v")]) + [(set_attr "type" "fpload,fpload,fpload,load") + (set_attr "length" "8") + (set_attr "isa" "*,p7v,p9v,*")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" @@ -3647,25 +3608,6 @@ } [(set_attr "type" "fpload,load")]) -;; V4SF extract from memory with variable element number and convert to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload")]) - ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") @@ -4023,90 +3965,6 @@ (set_attr "length" "4,4,8,4,8") (set_attr "isa" "*,*,*,,")]) -;; Fold extracting a V4SI element with a constant element with either sign or -;; zero extension to DImode. -;; Alternatives: -;; 1: GPR, element 0, normal address, no modification -;; 2: GPR, element 0-3, offsettable address -;; 3: GPR, element 0-3, single register (offset to op[3]) -;; 4: VSX, element 0, X-form address, no modification -;; 5: VSX, element 0-3, single register (offset to op[3]) -(define_insn_and_split "*vsx_extract_v4si_load_to_di" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa") - (any_extend:DI - (vec_select:SI - (match_operand:V4SI 1 "memory_operand" "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (any_extend:DI (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - SImode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8")]) - -;; Fold extracting a V8HI/V4SI element with a constant element with zero -;; extension to either DImode or SImode. -;; Alternatives: -;; 1: GPR, element 0, normal address, no modification -;; 2: GPR, element 0-3, offsettable address -;; 3: GPR, element 0-3, single register (offset to op[3]) -;; 4: VMX, element 0, X-form address, no modification -;; 5: VMX, element 0-3, single register (offset to op[3]) -(define_insn_and_split "*vsx_extract__load_to_u" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v") - (zero_extend:GPR - (vec_select: - (match_operand:VSX_EXTRACT_I2 1 "memory_operand" - "m,o,m,Z,Q") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (zero_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); -} - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "*,*,8,*,8") - (set_attr "isa" "*,*,*,p9v,p9v")]) - -;; Fold extracting a V8HI element with a constant element with sign extension -;; to either DImode or SImode. -;; Alternatives: -;; 1: GPR, element 0, normal address, no modification -;; 2: GPR, element 0-3, offsettable address -;; 3: GPR, element 0-3, single register (offset to op[3]) -(define_insn_and_split "*vsx_extract_v8hi_load_to_s" - [(set (match_operand:GPR 0 "register_operand" "=r,r,r") - (sign_extend:GPR - (vec_select:HI - (match_operand:V8HI 1 "memory_operand" "m,o,m") - (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")])))) - (clobber (match_scratch:DI 3 "=X,X,&b"))] - "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (sign_extend:GPR (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - HImode); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) - ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index 61f021ee99f..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_element_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index 4670e261ba8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include - -void -extract_v4sf_gpr_0 (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -void -extract_v4sf_gpr_1 (vector float *p, float *q) -{ - float x = vec_extract (*p, 1); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c deleted file mode 100644 index 2561aa930b6..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c +++ /dev/null @@ -1,22 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include -#include - -void -extract_v4sf_gpr_n (vector float *p, float *q, size_t n) -{ - float x = vec_extract (*p, n); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index e59ceae6866..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_0_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_3_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 3); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index 052371e72ef..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index 65ae21b1a1c..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c deleted file mode 100644 index 6a2f23cfc57..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_0_index_4 (vector short *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_3_index_4 (vector short *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */