From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 8640A3858D37; Sat, 29 Apr 2023 00:09:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8640A3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682726944; bh=DU+nIboP68TOJ7dzharGCOL2b37aoupafQ9olJEFnhU=; h=From:To:Subject:Date:From; b=lH/e3mrjidyl+f6Rm2ILKYTCSHTgf6i0nO6FCA3mHODuFWv+bbz4yHkpWcbSDKfIY HRuhH3zMu1POMt90NKToDKajCg9koU1vlUp4O8kS/ZaS3BiXgaabcZY+rALzz225Eu giBC1mHglJoG/jUFP2GeTe7/6GuL7wCkHDTtOZuY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Optimize vec_extract of V4SF with variable element number being converted to DF X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 590d55ae10495faf15ffaf122205d095eb3aa440 X-Git-Newrev: eaa7e53f55d4adc2b4abafa4123c11924024ff46 Message-Id: <20230429000904.8640A3858D37@sourceware.org> Date: Sat, 29 Apr 2023 00:09:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:eaa7e53f55d4adc2b4abafa4123c11924024ff46 commit eaa7e53f55d4adc2b4abafa4123c11924024ff46 Author: Michael Meissner Date: Fri Apr 28 20:08:46 2023 -0400 Optimize vec_extract of V4SF with variable element number being converted to DF This patch adds a combiner insn to include the conversion of float to double within the memory address when vec_extract of V4SF with a variable element number is done. 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_var_load_to_df): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-float-2.c: New file. Diff: --- gcc/config/rs6000/vsx.md | 19 +++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-float-2.c | 22 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ce00e8a1db6..60e686f2bfa 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3667,6 +3667,25 @@ } [(set_attr "type" "fpload,load")]) +;; V4SF extract from memory with variable element number and convert to DFmode. +(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" + [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") + (float_extend:DF + (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT))) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (float_extend:DF (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload")]) + ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c new file mode 100644 index 00000000000..2561aa930b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with variable element numbers can load + float elements into a GPR register without doing a LFS/STFS. */ + +#include +#include + +void +extract_v4sf_gpr_n (vector float *p, float *q, size_t n) +{ + float x = vec_extract (*p, n); + __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ + *q = x; +} + +/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ +/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */