From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E84FC3858D37; Sat, 29 Apr 2023 00:47:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E84FC3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682729258; bh=1IdHFyqwq1pJXvlV3iSZ9iwIXxmDeqRDCfdvyIzJj7U=; h=From:To:Subject:Date:From; b=ckr3yhr93MChn9+W5BQHrP7N18ARU8A+uoOHooi27rBjcLNZ7db3sR26z6nDmAAI2 dDKBvgNI3O9DWfOPerGiPD3s/fbtP0mYA2y9CZZpBuD6f5a+evCb0gEZU3KrDmzH0V U0MHKM0MO7Ao47/NWE/SyWLEpTmO/pfmJ2c3GJso= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: eaa7e53f55d4adc2b4abafa4123c11924024ff46 X-Git-Newrev: 371e826e204a8063d66b8ee92d4fcbe4499f5366 Message-Id: <20230429004738.E84FC3858D37@sourceware.org> Date: Sat, 29 Apr 2023 00:47:38 +0000 (GMT) List-Id: https://gcc.gnu.org/g:371e826e204a8063d66b8ee92d4fcbe4499f5366 commit 371e826e204a8063d66b8ee92d4fcbe4499f5366 Author: Michael Meissner Date: Fri Apr 28 20:47:17 2023 -0400 Allow consant element vec_extract to be zero or sign extended This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be zero extended. It also allows vec_extract of V4SI and V8HI vector types with constant element number to be sign extended. 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (vsx_extract_v4si_load_to_di): New insn. (vsx_extract__load_to_u): New insn. (vsx_extract_v8hi_load_to_s): New insn. gcc/testsuite/ * gcc.target/powerpc/vec-extract-mem-char-1.c: New file. * gcc.target/powerpc/vec-extract-mem-int-1.c: New file. * gcc.target/powerpc/vec-extract-mem-int-2.c: New file. * gcc.target/powerpc/vec-extract-mem-short-1.c: New file. * gcc.target/powerpc/vec-extract-mem-short-2.c: New file. Diff: --- .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 +++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 +++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-int-2.c | 36 ++++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 +++++++++++++++++++++ .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 ++++++++++++++++++++++ 5 files changed, 177 insertions(+) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c new file mode 100644 index 00000000000..61f021ee99f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + QImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v16qi_element_0 (vector unsigned char *p) +{ + return vec_extract (*p, 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_1 (vector unsigned char *p) +{ + return vec_extract (*p, 1); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) +{ + return vec_extract (p[4], 3); /* lbz, no rlwinm. */ +} + +/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c new file mode 100644 index 00000000000..e59ceae6866 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v4si_0 (vector unsigned int *p) +{ + return vec_extract (*p, 0); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_1 (vector unsigned int *p) +{ + return vec_extract (*p, 1); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_element_0_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 0); /* lwz, no rldicl. */ +} + +unsigned long long +extract_uns_v4si_element_3_index_4 (vector unsigned int *p) +{ + return vec_extract (p[4], 3); /* lwz, no rldicl. */ +} + +/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c new file mode 100644 index 00000000000..052371e72ef --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold sign extension into the load. */ + +#include + +long long +extract_sign_v4si_0 (vector int *p) +{ + return vec_extract (*p, 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_1 (vector int *p) +{ + return vec_extract (*p, 1); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_element_0_index_4 (vector int *p) +{ + return vec_extract (p[4], 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v4si_element_3_index_4 (vector int *p) +{ + return vec_extract (p[4], 3); /* lwa, no extsw. */ +} + +/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */ +/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c new file mode 100644 index 00000000000..65ae21b1a1c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + SImode and fold zero extension into the load. */ + +#include + +unsigned long long +extract_uns_v8hi_0 (vector unsigned short *p) +{ + return vec_extract (*p, 0); /* lwz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_1 (vector unsigned short *p) +{ + return vec_extract (*p, 1); /* lwz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 0); /* lbz, no rlwinm. */ +} + +unsigned long long +extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) +{ + return vec_extract (p[4], 3); /* lbz, no rlwinm. */ +} + +/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c new file mode 100644 index 00000000000..6a2f23cfc57 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +/* Test to verify that the vec_extract with constant element numbers can load + HImode and fold sign extension into the load. */ + +#include + +long long +extract_sign_v8hi_0 (vector short *p) +{ + return vec_extract (*p, 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_1 (vector short *p) +{ + return vec_extract (*p, 1); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_element_0_index_4 (vector short *p) +{ + return vec_extract (p[4], 0); /* lwa, no extsw. */ +} + +long long +extract_sign_v8hi_element_3_index_4 (vector short *p) +{ + return vec_extract (p[4], 3); /* lwa, no extsw. */ +} + +/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */ +/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */ +/* { dg-final { scan-assembler-not {\mextsh\M} } } */