From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 8259F3858D37; Sat, 29 Apr 2023 01:28:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8259F3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682731707; bh=jS0Oi5NgIDTcF/NSPI7lVzSneO+r42aZAguoycOFTpA=; h=From:To:Subject:Date:From; b=r6P4gvK0zx+hIrJ4HX9HaVuJ+xIwDhB3Kdv4GUm56kQTlmRjQ+J3+OtSyG6FmEWM+ UV/CDwFTAI4M3qyTFvjcwkd3taeZAyugGV5EJFTKzmwF8UhC+bvh5fmBpoY10CAKw1 Chetj6jAa6OK2iYzbqFL+p+aWXViE0HFH0sEB+WY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Revert patches X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 371e826e204a8063d66b8ee92d4fcbe4499f5366 X-Git-Newrev: 20d3a09037cd05d36fc9d73eae93fb75dead73bc Message-Id: <20230429012827.8259F3858D37@sourceware.org> Date: Sat, 29 Apr 2023 01:28:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:20d3a09037cd05d36fc9d73eae93fb75dead73bc commit 20d3a09037cd05d36fc9d73eae93fb75dead73bc Author: Michael Meissner Date: Fri Apr 28 21:28:23 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/vsx.md | 127 +++------------------ .../gcc.target/powerpc/vec-extract-mem-char-1.c | 35 ------ .../gcc.target/powerpc/vec-extract-mem-float-1.c | 29 ----- .../gcc.target/powerpc/vec-extract-mem-float-2.c | 22 ---- .../gcc.target/powerpc/vec-extract-mem-int-1.c | 35 ------ .../gcc.target/powerpc/vec-extract-mem-int-2.c | 36 ------ .../gcc.target/powerpc/vec-extract-mem-int-3.c | 0 .../gcc.target/powerpc/vec-extract-mem-short-1.c | 35 ------ .../gcc.target/powerpc/vec-extract-mem-short-2.c | 36 ------ .../gcc.target/powerpc/vec-extract-mem-short-3.c | 0 10 files changed, 16 insertions(+), 339 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 60e686f2bfa..417aff5e24b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,12 +223,6 @@ (V8HI "v") (V4SI "wa")]) -;; Mode attribute to give the isa constraint for accessing Altivec registers -;; with vector extract and insert operations. -(define_mode_attr VSX_EX_ISA [(V16QI "p9v") - (V8HI "p9v") - (V4SI "p8v")]) - ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3555,33 +3549,12 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) -;; V4SF extract from memory with constant element number. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -;; 8: GPR 0 any normal address no -;; 9: GPR 0-3 any offsettable address no -;; 10: GPR 0-3 any single register yes (define_insn_and_split "*vsx_extract_v4sf_load" - [(set (match_operand:SF 0 "register_operand" - "=f, f, f, v, v, v, v, - ?r, ?r, ?r") + [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o, - m, o, Q") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "O, n, n, O, n, O, n, - O, n, n")]))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X, - X, X, &b"))] + (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) + (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" "&& reload_completed" @@ -3590,47 +3563,9 @@ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload, - load, load, load") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v, - *, *, *")]) - -;; V4SF extract from memory with constant element number and convert to DFmode. -;; Alternatives: -;; Reg: Ele: Cpu: Addr: need scratch -;; 1: FPR 0 any normal address no -;; 2: FPR 1-3 any offsettable address no -;; 3: FPR 1-3 any single register yes -;; 4: VMX 0 p8 reg+reg or reg no -;; 5: VMX 1-3 p8 single register yes -;; 6: VMX 0 p9 normal address no -;; 7: VMX 1-3 p9 offsettable address no -(define_insn_and_split "*vsx_extract_v4sf_load_to_df" - [(set (match_operand:DF 0 "register_operand" - "=f, f, f, v, v, v, v") - (float_extend:DF - (vec_select:SF - (match_operand:V4SF 1 "memory_operand" - "m, o, Q, Z, Q, m, o") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" - "=X, X, &b, X, &b, X, X")])))) - (clobber (match_scratch:P 3 - "=X, X, &b, X, &b, X, X"))] - "VECTOR_MEM_VSX_P (V4SFmode)" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" - "fpload, fpload, fpload, fpload, fpload, fpload, fpload") - (set_attr "isa" - "*, *, *, p8v, p8v, p9v, p9v")]) + [(set_attr "type" "fpload,fpload,fpload,load") + (set_attr "length" "8") + (set_attr "isa" "*,p7v,p9v,*")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" @@ -3667,25 +3602,6 @@ } [(set_attr "type" "fpload,load")]) -;; V4SF extract from memory with variable element number and convert to DFmode. -(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df" - [(set (match_operand:DF 0 "gpc_reg_operand" "=wa") - (float_extend:DF - (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_VSX_EXTRACT))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (float_extend:DF (match_dup 4)))] -{ - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], SFmode); -} - [(set_attr "type" "fpload")]) - ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") @@ -4014,34 +3930,23 @@ } [(set_attr "type" "mfvsr")]) -;; Extract a V16QI/V8HI/V4SI element from memory with a constant element -;; number. For vector registers, we require X-form addressing. -;; Alternatives: -;; 1: GPR, element 0, normal address -;; 2: GPR, element 0-n, offsettable address (fold offset) -;; 3: GPR, element 0-n, single register (op[3] has offset) -;; 4: FP/VMX, element 0, X-form address -;; 5: FP/VMX, element 0-n, single register (op[3] has offset) +;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" - "=r,r,r,,") + [(set (match_operand: 0 "register_operand" "=r") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") - (parallel - [(match_operand:QI 2 "" "O,n,n,O,n")]))) - (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") + (parallel [(match_operand:QI 2 "" "n")]))) + (clobber (match_scratch:DI 3 "=&b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], - operands[2], operands[3], - mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); } - [(set_attr "type" "load,load,load,fpload,fpload") - (set_attr "length" "4,4,8,4,8") - (set_attr "isa" "*,*,*,,")]) + [(set_attr "type" "load") + (set_attr "length" "8")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c deleted file mode 100644 index 61f021ee99f..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - QImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v16qi_element_0 (vector unsigned char *p) -{ - return vec_extract (*p, 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_1 (vector unsigned char *p) -{ - return vec_extract (*p, 1); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_0_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v16qi_element_3_index_4 (vector unsigned char *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c deleted file mode 100644 index 4670e261ba8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include - -void -extract_v4sf_gpr_0 (vector float *p, float *q) -{ - float x = vec_extract (*p, 0); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -void -extract_v4sf_gpr_1 (vector float *p, float *q) -{ - float x = vec_extract (*p, 1); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c deleted file mode 100644 index 2561aa930b6..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c +++ /dev/null @@ -1,22 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with variable element numbers can load - float elements into a GPR register without doing a LFS/STFS. */ - -#include -#include - -void -extract_v4sf_gpr_n (vector float *p, float *q, size_t n) -{ - float x = vec_extract (*p, n); - __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */ - *q = x; -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */ -/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c deleted file mode 100644 index e59ceae6866..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v4si_0 (vector unsigned int *p) -{ - return vec_extract (*p, 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_1 (vector unsigned int *p) -{ - return vec_extract (*p, 1); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_0_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 0); /* lwz, no rldicl. */ -} - -unsigned long long -extract_uns_v4si_element_3_index_4 (vector unsigned int *p) -{ - return vec_extract (p[4], 3); /* lwz, no rldicl. */ -} - -/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrldicl\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c deleted file mode 100644 index 052371e72ef..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v4si_0 (vector int *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_1 (vector int *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_0_index_4 (vector int *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v4si_element_3_index_4 (vector int *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c deleted file mode 100644 index 65ae21b1a1c..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - SImode and fold zero extension into the load. */ - -#include - -unsigned long long -extract_uns_v8hi_0 (vector unsigned short *p) -{ - return vec_extract (*p, 0); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_1 (vector unsigned short *p) -{ - return vec_extract (*p, 1); /* lwz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_0_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 0); /* lbz, no rlwinm. */ -} - -unsigned long long -extract_uns_v8hi_element_3_index_4 (vector unsigned short *p) -{ - return vec_extract (p[4], 3); /* lbz, no rlwinm. */ -} - -/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c deleted file mode 100644 index 6a2f23cfc57..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c +++ /dev/null @@ -1,36 +0,0 @@ -/* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ - -/* Test to verify that the vec_extract with constant element numbers can load - HImode and fold sign extension into the load. */ - -#include - -long long -extract_sign_v8hi_0 (vector short *p) -{ - return vec_extract (*p, 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_1 (vector short *p) -{ - return vec_extract (*p, 1); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_0_index_4 (vector short *p) -{ - return vec_extract (p[4], 0); /* lwa, no extsw. */ -} - -long long -extract_sign_v8hi_element_3_index_4 (vector short *p) -{ - return vec_extract (p[4], 3); /* lwa, no extsw. */ -} - -/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */ -/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */ -/* { dg-final { scan-assembler-not {\mextsh\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c deleted file mode 100644 index e69de29bb2d..00000000000