From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D24553858D37; Sat, 29 Apr 2023 03:11:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D24553858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682737902; bh=zwstVh9zXDQEH/9J6pewRGXzAvQab5AUOtKTV5aZNYE=; h=From:To:Subject:Date:From; b=WXb9TzozKHmPDHA8S0JKCOWzj7tzxM6G5x+ryIYckM8zvf8TEeSIbRPFzYgdrIeyr 0QSKGLjaPwichSalXGM9FIeyzpwXjJwqRrQMhrjTLvJdFD3P3NaayhLevZBWwK0qBZ dgPIByHKt2kSxMV0ygHXP9HT10ivDi40m430Y48M= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work119 X-Git-Oldrev: 3edb1d030892c4074609494f626cba437eaa6ae7 X-Git-Newrev: 404f0dd14879585ae9625c3714d7f58190074af3 Message-Id: <20230429031142.D24553858D37@sourceware.org> Date: Sat, 29 Apr 2023 03:11:42 +0000 (GMT) List-Id: https://gcc.gnu.org/g:404f0dd14879585ae9625c3714d7f58190074af3 commit 404f0dd14879585ae9625c3714d7f58190074af3 Author: Michael Meissner Date: Fri Apr 28 23:11:24 2023 -0400 Allow consant element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be loaded into vector registers directly. This patch also adds support for optimzing 0 element number to not need a base register tempoary. Likewise, if we have an offsettable address, we don't need to allocate a scratch register. 2023-04-28 Michael Meissner gcc/ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. (vsx_extract__load): Allow vector registers to be loaded. Add optimizations for loading up element 0 and/or with an offsettable address. Diff: --- gcc/config/rs6000/vsx.md | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f42793fe012..0118d4788cb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -4008,23 +4014,37 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element +;; number. For vector registers, we require X-form addressing. +;; Alternatives: +;; Reg: Ele: Cpu: Addr: need scratch +;; 1: GPR 0 any normal address no +;; 2: GPR 1-3 any offsettable address no +;; 3: GPR 1-3 any single register yes +;; 4: wa/v 0 p8/p9 reg+reg or reg no +;; 5: wa/v 1-3 p8/p9 single register yes (define_insn_and_split "*vsx_extract__load" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" + "=r, r, r, , ") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" + "m, o, m, Z, Q") + (parallel [(match_operand:QI 2 "" + "O, n, n, O, n")]))) + (clobber (match_scratch:DI 3 + "=X, X, &b, X, &b"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load, load, load, fpload, fpload") + (set_attr "length" "*, *, 8, *, 8") + (set_attr "isa" "*, *, *, , ")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var"